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SBAS308A− MAY 2004 − REVISED MARCH 2005
TIMING CHARACTERISTICS
N + 3
N + 4
N + 2
Sample
N
Analog
Input
N + 1
N + 17
N + 16
N + 14
N + 15
Signal
tA
Input Clock
tSTART
t
= t
+ t
PDI START SETUP
Output Clock
tSETUP
Data Out
(D0−D13)
N − 17
N − 16
N − 15
END
N − 14
N − 13
N − 3
N − 2
N − 1
Data Invalid
N
t
tHOLD
16.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS(1)(2)
Typical values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 80MSPS, 50% clock duty cycle, AVDD
=
DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted.(2)
PARAMETER
Switching Specification
Aperture delay, tA
DESCRIPTION
MIN
TYP
MAX
UNIT
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
1
300
4.2
3
ns
fs
Aperture jitter (uncertainty)
Data setup time, tSETUP
Data hold time, tHOLD
Data valid(3) to 50% of CLKOUT rising edge
50% of CLKOUT rising edge to data becoming invalid(3)
3.2
1.8
ns
ns
Input clock to output data valid
Input clock to Data valid start delay
Input clock to Data valid end delay
3.8
11
5
ns
ns
(4)
start, tSTART
Input clock to output data valid end,
8.4
(4)
tEND
Data rise time, tRISE
Data fall time, tFALL
Data rise time measured from 20% to 80% of DRVDD
Data fall time measured from 80% to 20% of DRVDD
5.6
4.4
6.1
5.1
ns
ns
Output enable (OE) to data output
delay
Time required for outputs to have stable timings with regard to Input
Clock(5) after OE is activated
Clock
Cycles
1000
(1)
Timing parameters are ensured by design and characterization, and not tested in production.
See Table 5 in the Application Information section for timing information at additional sampling frequencies.
Data valid refers to 2.0V for LOGIC HIGH and 0.8V for LOGIC LOW.
Refer to the Output Information section for details on using the input clock for data capture.
Data outputs are available within a clock from assertion of OE; however it takes 1000 clock cycles to ensure stable timing with respect to input
clock.
(2)
(3)
(4)
(5)
6
BB [ BURR-BROWN CORPORATION ]
