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SBAS308A− MAY 2004 − REVISED MARCH 2005
tSLOADS
tSLOADH
SEN
tWSCLK
tWSCLK
tSCLK
SCLK
tOS
tOH
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
(1)
MIN
(1)
TYP
(1)
MAX
SYMBOL
PARAMETER
SCLK Period
UNIT
ns
tSCLK
tWSCLK
tSLOADS
tSLOADH
tDS
50
25
8
SCLK Duty Cycle
SEN to SCLK setup time
SCLK to SEN hold time
Data Setup Time
50
75
%
ns
6
ns
8
ns
tDH
Data Hold Time
6
ns
(1)
Typ, min, and max values are characterized, but not production tested.
Table 2. Serial Register Table
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
0 0 0 0 0 0 0
D1
D0
DESCRIPTION
1
1
1
0
0
TP<1> TP<0>
0
0
TP<1:0> − Test modes for output data capture
TP<1:0> = 00: Normal mode of operation
TP<1:0> = 01: All outputs forced to 0
TP<1:0> = 10: All outputs forced to 1
TP<1:0> = 11: Each output bit toggles between 0 and
1. There is no ensured relationship between the bits
See Note 2
1
1
1
1
PDN
0
0
0
0
0
0
0
0
0
0
0
PDN = 0 : Normal mode of operation, PDN = 1 :
Device is put in power down (low current) mode
(1)
(2)
All register contents default to zero on reset.
The patterns given are applicable to the straight offset binary output format. If 2’s complement output format is selected, the test mode outputs
will be the 2’s complement equivalent of these patterns.
Table 3. DATA FORMAT SELECT (DFS TABLE)
DFS-PIN VOLTAGE (V
)
DATA FORMAT
CLOCK OUTPUT POLARITY
DFS
2
12
Straight Binary
Data valid on rising edge
V
t
AV
DD
DFS
5
12
4
12
2’s Complement
Straight Binary
2’s Complement
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
AV
AV
t V
t V
u
t
t
AV
AV
DD
DD
DD
DD
DFS
8
12
7
12
DFS
10
V
AV
DD
DFS
12
8
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