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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
between the 6X clock and the output data for optimum
capture. A 1X clock is also generated by the serializer and
transmitted by the LVDS buffer. The 1X clock (referred to
as ADCLKP/ADCLKN) is used to determine the start of the
12-bit data frame. The sync mode (enabled through a
register setting) gives out a data of six 0s followed by six
1s. Using this mode, the 1X clock can be used to determine
the start of the data frame. In addition to the deskew mode
pattern and the sync pattern, a custom pattern can be
defined by the user and output from the LVDS buffer.
It is recommended that the isolation be maintained on
board by using separate supplies to drive AVDD and
LVDD, as well as separate ground planes for AVSS and
LVSS.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The current in
the LVDS buffer is independent of the direction of
switching. Also, the low output swing as well as the
differential nature of the LVDS buffer results in low-noise
coupling.
POWER-DOWN MODE
NOISE COUPLING ISSUES
The ADS52763 has a power-down pin, PD. Pulling PD
high causes the devices to enter the power-down mode. In
this mode, the reference and clock circuitry as well as all
the channels are powered down. Device power
consumption drops to less than 100mW in this mode.
Individual channels can also be selectively powered down
by programming registers.
High-speed mixed signals are sensitive to various types of
noise coupling. One of the main sources of noise is the
switching noise from the serializer and the output buffers.
Maximum care is taken to isolate these noise sources from
the sensitive analog blocks. As a starting point, the analog
and digital domains of the chip are clearly demarcated.
AVDD and AVSS are used to denote the supplies for the
analog sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there is
minimal interaction between the supply sets within the
device. The extent of noise coupled and transmitted from
the digital to the analog sections depends on the following:
The ADS5273 also has an internal circuit that monitors the
state of stopped clocks. If ADCLK is stopped (or if it runs
at a speed < 3MHz), this monitoring circuit generates a
logic signal that puts the device in a power-down state. As
a result, the power consumption of the device goes to less
than 100mW when ADCLK is stopped. This circuit can
also be disabled using register options.
1. The effective inductances of each of the
supply/ground sets.
SUPPLY SEQUENCE
2. The isolation between the digital and analog
supply/ground sets.
The following supply sequence is recommended for
powering up the device:
Smaller effective inductance of the supply/ground pins
leads to better suppression of the noise. For this reason,
multiple pins are used to drive each supply/ground. It is
also critical to ensure that the impedances of the supply
and ground lines on board are kept to the minimum
possible values. Use of ground planes in the board as well
as large decoupling capacitors between the supply and
ground lines are necessary to get the best possible SNR
from the device.
1. AVDD is powered up.
2. LVDD is powered up.
After the supplies have stabilized, the device must receive
an active RESET pulse. This results in all internal registers
getting reset to their default value of 0 (inactive). Without
RESET, it is possible that some registers might be in their
non-default state on power-up. This could cause the
device to malfunction.
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