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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
Another critical specification is the aperture jitter that is
defined as the uncertainty of the sampling instant. The
gates in the clock path are designed so as to give an rms
jitter of about 1ps.
REFERENCE CIRCUIT DESIGN
The digital beam-forming algorithm relies heavily on gain
matching across all receiver channels. A typical system
would have about 12 octal ADCs on the board. In such a
case, it is critical to ensure that the gain is matched,
essentially requiring the reference voltages seen by all the
ADCs to be the same. Matching references within the eight
channels of a chip is done by using a single internal
reference voltage buffer. Trimming the reference voltages
on each chip during production ensures the reference
voltages are well matched across different chips.
The input ADCLK should ideally have a 50% duty cycle.
However, while routing ADCLK to different components on
board, the duty cycle of the ADCLK reaching the ADS5273
could deviate from 50%. A smaller (or larger) duty cycle
eats into the time available for sample or hold phases of
each circuit, and is therefore not optimal. For this reason,
the internal PLL is used to generate an internal clock that
has 50% duty cycle.
All bias currents required for the internal operation of the
device are set using an external resistor to ground at pin
ISET. Using a 56kΩ resistor on ISET generates an internal
reference current of 20µA. This current is mirrored
internally to generate the bias current for the internal
blocks. Using a larger external resistor at ISET reduces the
reference bias current and thereby scales down the device
operating power. However, it is recommended that the
external resistor be within 10% of the specified value of
56k so that the internal bias margins for the various blocks
are proper.
The use of the PLL automatically dictates the lower
frequency of operation to be about 20MHz.
LVDS BUFFERS
The LVDS buffer has two current sources, as shown in
Figure 2. OUTP and OUTN are loaded externally by a
resistive load that is ideally about 100Ω. Depending on the
data being 0 or 1, the currents are directed in one or the
other direction through the resistor. The LVDS buffer has
four current settings. The default current setting is 3.5mA,
and gives a differential drop of about 350mV across the
100Ω resistor.
Buffering the internal bandgap voltage also generates a
voltage called VCM, which is set to the midlevel of REFT
and REFB, and is accessible on a pin. The internal buffer
driving VCM has a drive of 4mA. It is meant as a reference
voltage to derive the input common-mode in case the input
is directly coupled.
The device also supports the use of external reference
voltages. This involves forcing REFT and REFB externally.
In this mode, the internal reference buffer is tri-stated.
Since the switching current for the eight ADCs come from
the externally forced references, it is possible for the
performance to be slightly less than when the internal
references are used. It should be noted that in this mode,
External
Termination
Resistor
High
Low
OUTP
OUTN
Low
High
V
CM and ISET continue to be generated from the internal
bandgap voltage, as in the internal reference mode. It is
therefore important to ensure that the common-mode
voltage of the externally forced reference voltages
matches to within 50mV of VCM
.
CLOCKING
Figure 2. LVDS Buffer
The eight channels on the chip run off a single ADCLK
input. To ensure that the aperture delay and jitter are same
for all the channels, a clock tree network is used to
generate individual sampling clocks to each channel. The
clock paths for all the channels are matched from the
source point all the way to the sample-and-hold. This
ensures that the performance and timing for all the
channels are identical. The use of the clock tree for
matching introduces an aperture delay, which is defined as
the delay between the rising edge of ADCLK and the actual
instant of sampling. The aperture delays for all the
channels are matched, and vary between 2.5ns to 4.5ns.
The LVDS buffer gets data from a serializer that takes the
output data from each channel and serializes it into a
single data stream. For a clock frequency of 40MHz, the
data rate output by the serializer is 480 MBPS. The data
comes out LSB first, with a register programmability to
revert to MSB first. The serializer also gives out a 1X clock
and a 6X clock. The 6X clock (denoted as LCLKP/ LCLKN)
is meant to synchronize the capture of the LVDS data. The
deskew mode can be enabled as well, using a register
setting. This mode gives out a data stream of alternate 0s
and 1s and can be used determine the relative delay
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