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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
DRIVING THE ANALOG INPUTS
THEORY OF OPERATION
The analog input biasing is shown in Figure 1. The
recommended method to drive the inputs is through AC
coupling. AC coupling removes the worry of setting the
common-mode of the driving circuit, since the inputs are
biased internally using two 600Ω resistors. The sampling
capacitor used to sample the inputs is 4pF. The choice of
the external AC coupling capacitor is dictated by the
attenuation at the lowest desired input frequency of
operation factor. The attenuation resulting from using a
10nF AC coupling capacitor is 0.04%.
OVERVIEW
The ADS5273 is an 8-channel, high-speed, CMOS ADC,
consisting of a high-performance sample-and-hold circuit
at the input, followed by a 12-bit ADC. The 12 bits given out
by each channel are serialized and sent out on a single pair
of pins in LVDS format. All eight channels of the ADS5273
operate from a single clock referred to as ADCLK. The
sampling clock for each of the eight channels is generated
from the input clock using a carefully matched clock buffer
tree. The 12X clock required for the serializer is generated
internally from ADCLK using a phase lock loop (PLL). A 6X
and a 1X clock are also output in LVDS format along with
the data to enable easy data capture. The ADS5273
operates from an internally generated reference voltage
that is trimmed to ensure matching across multiple devices
on a board. This feature eliminates the need for external
routing of reference lines and also improves matching of
the gain across devices. The nominal values of REFP and
REFN are 2V and 1V, respectively. These values imply that
a differential input of −1V corresponds to the zero code of
the ADC, and a differential input of +1V corresponds to the
full-scale code (4095 LSB). VCM (common-mode voltage
of REFP and REFN) is also made available externally
through a pin, and is nominally 1.5V.
ADS5273
IN+
Ω
Ω
600
Input
Circuitry
600
−
IN
CM Buffer 1
CM Buffer 2
Internal
Voltage
Reference
VCM
The ADC employs a pipelined converter architecture
consisting of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the digital
error correction logic, ensuring excellent differential
linearity and no missing codes at the 12-bit level. The
pipeline architecture results in a data latency of 6.5 clock
cycles.
Figure 1. Analog Input Bias Circuitry
If the input is DC coupled, then the output common-mode
voltage of the circuit driving the ADS5273 should match
the VCM (which is provided as an output pin) to within
50mV. It is recommended that the output common-mode
of the driving circuit be derived from VCM provided by the
device.
The output of the ADC goes to a serializer that operates
from a 12X clock generated by the PLL. The 12 data bits
from each channel are serialized and sent LSB first. In
addition to serializing the data, the serializer also
generates a 1X clock and a 6X clock. These clocks are
generated in the same way the serialized data is
generated, so these clocks maintain perfect synchroniza-
tion with the data. The data and clock outputs of the
serializer are buffered externally using LVDS buffers.
Using LVDS buffers to transmit data externally has
multiple advantages, such as a reduced number of output
pins (saving routing space on the board), reduced power
consumption, and reduced effects of digital noise coupling
to the analog circuit inside the ADS5273.
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale input peak-to-peak supported by
the ADS5273 is 2V. For a nominal value of VCM (1.5V), INP
and INN can swing from 1V to 2V. The ADS5273 is
specially designed to handle an over-voltage differential
peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP
and INN). If the input common-mode is not considerably off
from VCM during overload (less than 300mV), recovery
from an over-voltage input condition is expected to be
within 4 clock cycles. All of the amplifiers in the SHA and
ADC are especially designed for excellent recovery from
an overload signal.
The ADS5273 operates from two sets of supplies and
grounds. The analog supply/ground set is denoted as
AVDD/AVSS, while the digital set is denoted by
LVDD/LVSS.
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