ADS1610
www.ti.com
SBAS344C–AUGUST 2005–REVISED OCTOBER 2006
DATA FORMAT
OUT-OF-RANGE INDICATION (OTR)
The 16-bit output data is in binary two's complement
format, as shown in Table 2. When the input is
positive out-of-range, exceeding the positive
full-scale value of VREF, the output clips to all 7FFFH
and the OTR output goes high.
If the output code on DOUT[15:0] exceeds the
positive or negative full-scale, the out-of-range digital
output (OTR) will go high on the falling edge of
DRDY. When the output code returns within the
full-scale range, OTR returns low on the falling edge
of DRDY.
Table 1. Maximum Allowable Clock Source Jitter
for Different Input Signal Frequencies and
Amplitude
DATA RETRIEVAL
Data retrieval is controlled through a simple parallel
interface. The falling edge of the DRDY output
indicates new data is available. To activate the
output bus, both CS and RD must be low, as shown
in Table 3. Make sure the DOUT bus does not drive
heavy loads (> 20pF), as this will degrade
performance. Use an external buffer when driving an
edge connector or cables.
INPUT SIGNAL
MAXIMUM
ALLOWABLE
CLOCK SOURCE
JITTER
MAXIMUM
MAXIMUM
FREQUENCY
AMPLITUDE
4MHz
4MHz
2MHz
2MHz
1MHz
1MHz
100kHz
100kHz
–1dB
–20dB
–1dB
1.6ps
14ps
3.3ps
29ps
6.5ps
58ps
65ps
581ps
–20dB
–1dB
Table 3. Truth Table for CS and RD
–20dB
–1dB
CS
0
RD
0
DOUT [15:0]
Active
–20dB
0
1
High impedance
High impedance
High impedance
1
0
Table 2. Output Code Versus Input Signal
1
1
INPUT SIGNAL
(INP – INN)
IDEAL OUTPUT
CODE(1)
OTR
SYNCHRONISING MULTIPLE ADS1610s
≥ +Vref (> 0dB)
7FFFH
7FFFH
0001H
1
0
0
The ADS1610 is asynchronously reset when the
SYNC pin is taken low. During reset, all of the digital
circuits are cleared, DOUT[15:0] are forced low, and
DRDY forced high. It is recommended that the SYNC
pin be released on the falling edge of CLK.
Afterwards, DRDY goes low on the second rising
edge of CLK. Allow 55 DRDY cycles for the digital
filter to settle before retrieving data. See Figure 3 for
the timing specifications.
Vref (0dB)
) V
REF
215 * 1
0
0000H
FFFFH
0
0
*V
REF
215 * 1
215
215 * 1
8000H
8000H
0
1
REFǒ
Ǔ
*V
Reset can be used to synchronize multiple
ADS1610s. All devices to be synchronized must use
a common CLK input. With the CLK inputs running,
pulse SYNC on the falling edge of CLK, as shown in
Figure 31. Afterwards, the converters will be
converting synchronously with the DRDY outputs
updating simultaneously. After synchronization, allow
55 DRDY cycles (t11) for output data to fully settle.
215
215 * 1
REFǒ
Ǔ
v *V
(1)Excludes effects of noise, INL, offset and gain errors.
Likewise, when the input is negative out-of-range by
going below the negative full-scale value of Vref, the
output clips to 8000H and the OTR output goes high.
The OTR remains high while the input signal is
out-of-range.
15
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