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ADS1610IPAPTG4 参数 Datasheet PDF下载

ADS1610IPAPTG4图片预览
型号: ADS1610IPAPTG4
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 10 MSPS模拟数字转换器 [16-Bit, 10 MSPS ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 26 页 / 667 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ADS1610  
www.ti.com  
SBAS344CAUGUST 2005REVISED OCTOBER 2006  
driver circuits low-thermal noise in the driver circuits  
degrades the overall noise performance. When the  
signal can be AC-coupled to the ADS1610 inputs, a  
simple RC filter can set the input common mode  
ADS1610  
S1  
AINP  
voltage. The ADS1610 is  
a high-speed, high-  
S2  
performance ADC. Special care must be taken when  
selecting the test equipment and setup used with this  
device. Pay particular attention to the signal sources  
to ensure they do not limit performance when  
measuring the ADS1610.  
10pF  
8pF  
VMID  
S1  
AINN  
S2  
10pF  
8pF  
10pF  
ADS1610  
VMID  
787  
AGND  
374  
12.5  
12.5  
VIN  
AINP  
AINN  
Figure 25. Conceptual Diagram of Internal  
Circuitry Connected to the Analog Inputs  
100pF  
100pF  
56.2  
VCM  
THS4503  
374  
−VIN  
100pF  
787  
56.2  
tSAMPLE = 1/fCLK  
On  
Off  
S1  
S2  
10 pF  
On  
Off  
Figure 27. Recommended Single-Ended to  
Differential Conversion Circuit Using the  
THS4503 Differential Amplifier  
Figure 26. Timing for the Switches in Figure 25  
DRIVING THE INPUTS  
392  
The external circuits driving the ADS1610 inputs  
must be able to handle the load presented by the  
switching capacitors within the ADS1610. The input  
switches S1 in Figure 25 are closed approximately  
one half of the sampling period, tSAMPLE, allowing  
only ~8 ns for the internal capacitors to be charged  
by the inputs, when fCLK = 60MHz.  
20 pF  
392  
392  
V
IN  
2
µ
0.01  
F
12.5  
AINP  
OPA2822  
(2)  
(1)  
V
CM  
100pF  
1k  
µ
1 F  
392  
(2)  
Figure 27 and Figure 28 show the recommended  
circuits when using single-ended or differential op  
amps, respectively. The analog inputs must be  
driven differentially to achieve optimum performance.  
If only a single-ended input signal is available, the  
configuration in Figure 27 can be used by shorting  
–VIN to ground.  
392  
ADS1610  
(1)  
(3)  
100pF  
V
CM  
(2)  
20 pF  
392  
V
1k  
IN  
2
µ
F
0.01  
12.5  
AINN  
OPA2822  
392  
(2)  
(1)  
V
CM  
100pF  
µ
F
392  
1
This configuration would implement the single-ended  
to differential conversion.  
A GND  
The external capacitors, between the inputs and from  
each input to AGND, improve linearity and should be  
placed as close to the pins as possible. Place the  
drivers close to the inputs and use good capacitor  
bypass techniques on their supplies; usually a  
smaller high-quality ceramic capacitor in parallel with  
a larger capacitor. Keep the resistances used in the  
(1) Recommended VCM = 2.5V.  
(2) Optional accoupling circuit provides commonmode input voltage.  
(3) Increase to 390pF when fIN 100kHz for improved SNR and THD.  
Figure 28. Recommended Driver Circuit Using  
the OPA2822  
13  
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