ADS1274
ADS1278
www.ti.com
SBAS367–JUNE 2007
FORMAT[2:0]
Even though the SCLK input has hysteresis, it is
recommended to keep SCLK as clean as possible to
prevent glitches from accidentally shifting the data.
Data can be read from the ADS1274/78 with two
interface protocols (SPI or Frame-Sync) and several
options of data formats (TDM/Discrete and
Fixed/Dynamic data positions). The FORMAT[2:0]
inputs are used to select among the options. Table 12
lists the available options. See the DOUT Modes
section for details of the DOUT Mode and Data
Position.
SCLK may be run as fast as the CLK frequency.
SCLK may be either in free-running or stop-clock
operation between conversions. Note that one fCLK is
required after the falling edge of DRDY until the first
rising edge of SCLK. For best performance, limit
fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. When the
device is configured for modulator output, SCLK
becomes the modulator clock output (see the
Modulator Output section).
Table 12. Data Output Format
INTERFACE
PROTOCOL
DOUT
MODE
DATA
POSITION
FORMAT[2:0]
DRDY/FSYNC (SPI Format)
000
001
010
011
100
101
110
SPI
SPI
TDM
TDM
Dynamic
Fixed
—
In the SPI format, this pin functions as the DRDY
output. It goes low when data are ready for retrieval
and then returns high on the falling edge of the first
subsequent SCLK. If data are not retrieved (that is,
SCLK is held low), DRDY pulses high just before the
next conversion data are ready, as shown in
Figure 76. The new data are loaded within one CLK
cycle before DRDY goes low. All data must be shifted
out before this time to avoid being overwritten.
SPI
Discrete
TDM
Frame-Sync
Frame-Sync
Frame-Sync
Modulator Mode
Dynamic
Fixed
—
TDM
Discrete
—
—
SERIAL INTERFACE PROTOCOLS
Data are retrieved from the ADS1274/78 using the
serial interface. Two protocols are available: SPI and
Frame-Sync. The same pins are used for both
1/fCLK
1/fDATA
DRDY
interfaces:
SCLK,
DRDY/FSYNC,
DOUT[4:1]
SCLK
(DOUT[8:1] for ADS1278), and DIN. The
FORMAT[2:0] pins select the desired interface
protocol.
Figure 76. DRDY Timing with No Readback
SPI SERIAL INTERFACE
DOUT
The SPI-compatible format is a read-only interface.
Data ready for retrieval are indicated by the falling
DRDY output and are shifted out on the falling edge
of SCLK, MSB first. The interface can be
daisy-chained using the DIN input when using
multiple devices. See the Daisy-Chaining section for
more information.
The conversion data are output on DOUT[4:1]/[8:1].
The MSB data are valid on DOUT[4:1]/[8:1] after
DRDY goes low. Subsequent bits are shifted out with
each falling edge of SCLK. If daisy-chaining, the data
shifted in using DIN appear on DOUT after all
channel data have been shifted out. When the device
is configured for modulator output, DOUT[4:1]/[8:1]
becomes the modulator data output for each channel
(see the Modulator Output section).
NOTE: The SPI format is limited to a CLK input
frequency of 27MHz, maximum. For CLK input
operation above 27MHz (High-Speed mode only),
use Frame-Sync format.
DIN
This input is used when multiple ADS1274/78s are to
be daisy-chained together. The DOUT1 pin of the first
device connects to the DIN pin of the next, etc. It can
be used with either the SPI or Frame-Sync formats.
Data are shifted in on the falling edge of SCLK. When
using only one ADS1274/78, tie DIN low. See the
Daisy-Chaining section for more information.
SCLK
The serial clock (SCLK) features a Schmitt-triggered
input and shifts out data on DOUT on the falling
edge. It also shifts in data on the falling edge on DIN
when this pin is being used for daisy-chaining. The
device shifts data out on the falling edge and the user
normally shifts this data in on the rising edge.
30
Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS1274 ADS1278
BB [ BURR-BROWN CORPORATION ]
