ADS1274
ADS1278
www.ti.com
SBAS367–JUNE 2007
MODE[1:0]
Pins
ADS1274/78 Previous
Mode
New Mode
tNDR-SPI
Mode
SPI
DRDY
Protocol
New Mode
Valid Data Ready
tNDR-FS
Frame-Sync
Protocol
DOUT
New Mode
Valid Data on DOUT
Figure 72. Mode Change Timing
Table 8. New Data After Mode Change
SYMBOL
tNDR-SPI
tNDR-FS
DESCRIPTION
MIN
TYP
MAX
129
UNITS
Time for new data to be ready (SPI)
Time for new data to be ready (Frame-Sync)
Conversions (1/fDATA
Conversions (1/fDATA
)
)
127
128
SYNCHRONIZATION (SYNC)
See Figure 74 for the Frame-Sync format timing
requirement.
The ADS1274/78 can be synchronized by pulsing the
SYNC pin low and then returning the pin high. When
the pin goes low, the conversion process stops, and
the internal counters used by the digital filter are
reset. When the SYNC pin returns high, the
conversion process restarts. Synchronization allows
the conversion to be aligned with an external event,
such as the changing of an external multiplexer on
the analog inputs, or by a reference timing pulse.
After synchronization, indication of valid data
depends on whether SPI or Frame-Sync format was
used.
In the SPI format, DRDY goes high as soon as SYNC
is taken low; see Figure 73. After SYNC is returned
high, DRDY stays high while the digital filter is
settling. Once valid data are ready for retrieval,
DRDY goes low.
Because the ADS1274/78 converters operate in
parallel from the same master clock and use the
same SYNC input control, they are always in
synchronization with each other. The aperture match
among internal channels is typically less than 500ps.
However, the synchronization of multiple devices is
somewhat different. At device power-on, variations in
internal reset thresholds from device to device may
result in uncertainty in conversion timing.
In the Frame-Sync format, DOUT goes low as soon
as SYNC is taken low; see Figure 74. After SYNC is
returned high, DOUT stays low while the digital filter
is settling. Once valid data are ready for retrieval,
DOUT begins to output valid data. For proper
synchronization, FSYNC, SCLK, and CLK must be
established before taking SYNC high, and must then
remain running. If the clock inputs (CLK, FSYNC or
SCLK) are subsequently interrupted or reset,
re-assert the SYNC pin.
The SYNC pin can be used to synchronize multiple
devices to within the same CLK cycle. Figure 73
illustrates the timing requirement of SYNC and CLK
in SPI format.
For consistent performance, re-assert SYNC after
device power-on when data first appear.
27
Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS1274 ADS1278
BB [ BURR-BROWN CORPORATION ]
