ADS1274
ADS1278
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SBAS367–JUNE 2007
Table 6. Clock Input Options
ESD diodes protect the reference inputs. To keep
these diodes from turning on, make sure the voltages
on the reference pins do not go below AGND by
more than 0.4V, and likewise do not exceed AVDD by
0.4V. If these conditions are possible, external
Schottky clamp diodes or series resistors may be
required to limit the input current to safe values (see
the Absolute Maximum Ratings table).
MODE
MAX fCLK
(MHz)
DATA RATE
(SPS)
SELECTION
CLKDIV fCLK/fDATA
High-Speed
32.768
27
1
1
1
0
1
0
256
512
128,000
52,734
High-Resolution
27
512
Low-Power
Low-Speed
52,734
10,547
13.5
27
256
2,560
512
Note that the valid operating range of the reference
inputs is limited to the following parameters:
5.4
MODE SELECTION (MODE)
–0.1V ≤ VREFN ≤ +0.1V
The ADS1274/78 supports four modes of operation:
High-Speed, High-Resolution, Low-Power, and
Low-Speed. The modes offer optimization of speed,
resolution, and power. Mode selection is determined
by the status of the digital input MODE[1:0] pins, as
shown in Table 7. The ADS1274/78 continually
monitors the status of the MODE pin during
operation.
VREFN + 0.5V ≤ VREFP ≤ AVDD + 0.1V
A high-quality reference voltage with the appropriate
drive strength is essential for achieving the best
performance from the ADS1274. Noise and drift on
the reference degrade overall system performance.
See the Application Information section for example
reference circuits.
CLOCK INPUT (CLK)
Table 7. Mode Selection
(1)
The ADS1274/78 requires a clock input for operation.
The individual converters of the ADS1274/78 operate
from the same clock input. At the maximum data rate,
the clock input can be either 27MHz or 13.5MHz for
Low-Power mode, or 27MHz or 5.4MHz for
Low-Speed mode, determined by the setting of the
CLKDIV input. For High-Speed mode, the maximum
MODE[1:0]
MODE SELECTION
High-Speed
MAX fDATA
128,000
52,734
00
01
10
11
High-Resolution
Low-Power
52,734
Low-Speed
10,547
(1) fCLK = 27MHz max (32.768MHz max in High-Speed mode).
CLK
input
frequency
is
32.768MHz.
For
High-Resolution mode, the maximum CLK input
frequency is 27MHz. The selection of the external
clock frequency (fCLK) does not affect the resolution of
the ADS1274/78. Use of a slower fCLK can reduce the
power consumption of an external clock buffer. The
output data rate scales with clock frequency, down to
a minimum clock frequency of fCLK = 100kHz. Table 6
summarizes the ratio of the clock input frequency
(fCLK) to data rate (fDATA), maximum data rate and
corresponding maximum clock input for the four
operating modes.
When using the SPI protocol, DRDY is held high after
a mode change occurs until settled (or valid) data are
ready; see Figure 72 and Table 8.
In Frame-Sync protocol, the DOUT pins are held low
after a mode change occurs until settled data are
ready; see Figure 72 and Table 8. Data can be read
from the device to detect when DOUT changes to
logic 1, indicating that the data are valid.
As with any high-speed data converter, a high-quality,
low-jitter clock is essential for optimum performance.
Crystal clock oscillators are the recommended clock
source. Make sure to avoid excess ringing on the
clock input; keeping the clock trace as short as
possible, and using a 50Ω series resistor placed
close to the source end, often helps.
26
Copyright © 2007, Texas Instruments Incorporated
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