ꢐꢕ ꢙꢚ ꢋ ꢛ ꢛ
ꢐꢕ ꢙꢚ ꢋ ꢛ ꢜ
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
CS
t3
t2H
t10
t1
SCLK
DIN
t4
t5
t6
t2L
t11
t7
t8
t9
DOUT
Figure 1. Serial Interface Timing
TIMING CHARACTERISTICS FOR FIGURE 1
SYMBOL DESCRIPTION
MIN
MAX
UNIT
(1)
4
τ
CLKIN
t
1
SCLK period
(2)
10
9
τ
DATA
ns
200
t
SCLK pulse width: high
2H
τ
DATA
t
200
0
ns
SCLK pulse width: low
2L
(3)
t
ns
ns
ns
CS low to first SCLK: setup time
3
t
50
50
Valid DIN to SCLK falling edge: setup time
Valid DIN to SCLK falling edge: hold time
4
t
5
Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,
RREG Commands
t
50
τ
τ
6
CLKIN
(4)
t
t
50
10
ns
ns
SCLK rising edge to valid new DOUT: propagation delay
7
0
6
SCLK rising edge to DOUT invalid: hold time
8
Last SCLK falling edge to DOUT high impedance
NOTE: DOUT goes high impedance immediately when CS goes high
t
9
CLKIN
ns
t
10
0
4
CS low after final SCLK falling edge
RREG, WREG, RDATA
τ
τ
CLKIN
24
RDATAC, RESET, SYNC
CLKIN
Final SCLK falling edge of command to first SCLK
t
11
RDATAC, STANDBY, SELFOCAL, SY-
SOCAL, SELFGCAL,
rising edge of next command.
Wait for DRDY to go low
SYSGCAL, SELFCAL
(1)
(2)
(3)
(4)
τ
= master clock period = 1/f .
CLKIN
= output data period 1/f .
DATA
CLKIN
τ
DATA
CS can be tied low.
DOUT load = 20pF 100kΩ to DGND.
6
BB [ BURR-BROWN CORPORATION ]
