As with the Master Mode of operation, when using SDIO as
edge of the last serial clock cycle of the instruction byte, the
SDIO pin will begin its transition from input to output.
Between six and eight XIN cycles after this falling edge, the
SDIO pin will become an output. This transition may be too
fast for some microcontrollers and digital signal processors.
Reset, Power-On Reset and Brown-Out
The ADS1212/13 contains an internal power-on reset cir-
cuit. If the power supply ramp rate is greater than 50mV/ms,
this circuit will be adequate to ensure the device powers up
correctly. (Due to oscillator settling considerations, commu-
nication to and from the ADS1212/13 should not occur for
at least 25ms after power is stable).
If a serial communication does not occur during any conver-
sion period, the ADS1212/13 will continue to operate prop-
erly. However, the results in the Data Output Register will be
lost when they are overwritten by the new result at the start of
the next conversion period. Just prior to this update, DRDY
will be forced HIGH and will return LOW after the update.
If this requirement cannot be met or if the circuit has
brown-out considerations, the timing diagram of Figure 27
can be used to reset the ADS1212/13. This timing applies
only when the ADS1212/13 is in the Slave Mode and
accomplishes the reset by controlling the duty cycle of the
SCLK input. In general, reset is required after power-up,
after a brown-out has been detected, or when a watchdog
timer event has occured.
Making Use of DSYNC
The DSYNC input pin and the DSYNC write bit in the
Command Register reset the current modulator count to
zero. This causes the current conversion cycle to proceed as
normal, but all modulator outputs from the last data output
to the point where DSYNC is asserted are discarded. Note
that the previous two data outputs are still present in the
ADS1212/13 internal memory. Both will be used to com-
pute the next conversion result, and the most recent one will
be used to compute the result two conversions later. DSYNC
does not reset the internal data to zero.
If the ADS1212/13 is in the Master Mode, a reset of the
device is not possible. If the power supply does not meet
the minimum ramp rate requirement or brown-out is of
concern, low on-resistance MOSFETs or equivalent should
be used to control power to the ADS1212/13. When pow-
ered down, the device should be left unpowered for at least
300ms before power is reapplied. An alternate method
would be to control the MODE pin and temporarily place
the ADS1212/13 in the Slave Mode while a reset is
initiated as shown in Figure 27.
There are two main uses of DSYNC. In the first case,
DSYNC allows for synchronization of multiple converters.
In regards to the DSYNC input pin, this case was discussed
under “Synchronizing Multiple Converters” in the Timing
section. In regards to the DSYNC bit, it will be difficult to
set all of the converter’s DSYNC bits at the same time
unless all of the converters are in the Slave Mode and the
same instruction can be sent to all of the converters at the
same time.
Two-Wire Interface
For a two-wire interface, the Master Mode of operation may
be preferable. In this mode, serial communication occurs
only when data is ready, informing the main controller as to
the status of the ADS1212/13. The disadvantages are that the
ADS1212/13 must have a dedicated serial port on the main
controller and only one instruction can be issued per data
ready period.
The second use of DSYNC is to reset the modulator count
to zero in order to obtain valid data as quickly as possible.
For example, if the input channel is changed on the ADS1213,
the current conversion cycle will be a mix of the old channel
and the new channels. Thus, four conversions are needed in
order to ensure valid data. However, if the channel is
changed and then DSYNC is used to reset the modulator
count, the modulator data at the end of the current conver-
sion cycle will be entirely from the new channel. After two
additional conversion cycles, the output data will be com-
pletely valid. Note that the conversion cycle in which
DSYNC is used will be slightly longer than normal. Its
length will depend on when DSYNC was set.
In the Slave Mode, the main controller must read and write
to the ADS1212/13 “blindly.” Writes to the internal regis-
ters, such as the Command Register or Offset Calibration
Register, might occur during an update of the Data Output
Register. This can result in invalid data in the DOR. A two-
wire interface can be used if the main controller can read
and/or write to the converter either much slower or much
faster than the data rate. For example, if much faster, the
main controller can use the DRDY bit to determine when
data is becoming valid (polling it multiple times during one
conversion cycle). Thus, the controller obtains some idea of
when to write to the internal registers. If much slower, then
reads of the DOR might always return valid data (mulitple
conversions have occurred since the last read of the DOR or
since any write of the internal registers).
t1: > 512 • tXIN
Reset occurs
< 800 • tXIN
at 2048 • tXIN
t2: > 10 • tXIN
t2
t2
t2
t3: > 1024 • tXIN
< 1800 • tXIN
SCLK
t4: ≥ 2048 • tXIN
< 2400 • tXIN
t3
t1
t3
t4
FIGURE 27. Resetting the ADS1212/13 (Slave Mode only).
ADS1212, 1213
30
SBAS064A
BB [ BURR-BROWN CORPORATION ]
