Start
Reading
ADS1212/13
drives DRDY LOW
From Read
Flowchart
Start
Writing
To Write
Flowchart
ADS1212/13
drives DRDY LOW
CS taken high
for 22 tXIN periods
minimum (see text
if CS tied LOW).
CS
state
HIGH
CS taken high
for 22 tXIN periods
minimum (see text
if CS tied low).
LOW
CS
state
Continuous
Read
Mode?
CS
state
HIGH
HIGH
Yes
LOW
External device
generates 8
serial clock cycles
and transmits
LOW
CS
state
No
HIGH
External device generates
8 serial clock cycles
LOW
and receives
transmits
instruction register
data via SDIO
instruction register
data via SDIO
External device
generates n
serial clock cycles
and transmits
specified
Use
SDIO for
output?
Yes
register data
via SDIO
No
SDOUT becomes
active
SDIO input to
output transition
ADS1212/13
drives DRDY HIGH
External device generates
n serial clock cycles
and receives
External device generates
n serial clock cycles
and receives
Yes
No
Is Next
Instruction
a Read?
More
Instructions?
specified register
data via SDOUT
specified register
data via SDIO
See text
for restrictions
No
Yes
SDOUT returns to
tri-state condition
SDIO transitions to
tri-state condition
End
To Read
Flowchart
ADS1212/13
drives DRDY HIGH
No
Is Next
Instruction
a Write?
Yes
More
Instructions?
See text
for restrictions
Yes
No
End
To Write
Flowchart
FIGURE 26. Flowchart for Writing and Reading Register Data, Slave Mode.
ADS1212, 1213
28
SBAS064A