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ADS1212PG4 参数 Datasheet PDF下载

ADS1212PG4图片预览
型号: ADS1212PG4
PDF下载: 下载PDF文件 查看货源
内容描述: 22位模拟数字转换器 [22-Bit ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 49 页 / 1227 K
品牌: BB [ BURR-BROWN CORPORATION ]
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SOURCE CURRENT  
A
IN3N  
AIN3P  
30  
25  
20  
15  
10  
5
+5V  
AIN2P  
AIN2N  
AIN1P  
AIN4N  
AIN4P  
R1  
49.9k  
40°C  
25°C  
85°C  
REFIN  
REFOUT  
AVDD  
REF1004  
+2.5V  
A
IN1N  
1.0µF  
+5V  
AGND  
VBIAS  
CS  
AVDD  
+5V  
ADS1213U, P  
MODE  
DRDY  
SDOUT  
SDIO  
+5V  
+5V  
VOH  
C1  
6pF  
DSYNC  
XIN  
VOH  
0V  
P1  
XTAL  
2kΩ  
XOUT  
DGND  
SCLK  
DVDD  
C2  
6pF  
+5V  
0
DGND  
0
1
2
3
4
5
DGND  
V
OH (V)  
FIGURE 34. Source Current vs VOH for SDOUT Under Worst-Case Conditions.  
SINK CURRENT  
30  
AIN3N  
AIN3P  
IN4N  
IN4P  
+5V  
A
A
A
A
IN2P  
IN2N  
IN1P  
IN1N  
A
25°C  
40°C  
R1  
49.9k  
25  
20  
15  
10  
5
A
REFIN  
REFOUT  
AVDD  
85°C  
REF1004  
+2.5V  
1.0µF  
0V  
AGND  
VBIAS  
CS  
AVDD  
+5V  
ADS1213U, P  
MODE  
DRDY  
SDOUT  
SDIO  
+5V  
C1  
+5V  
DSYNC  
XIN  
VOL  
6pF  
VOL  
0V  
P1  
2kΩ  
XTAL  
XOUT  
DGND  
SCLK  
C2  
DVDD  
+5V  
0
DGND  
6pF  
0
1
2
3
4
5
DGND  
V
OL (V)  
FIGURE 35. Sink Current vs VOL for SDOUT Under Worst-Case Conditions.  
Note that an asynchronous DSYNC input may cause mul-  
tiple converters to be different from one another by one XIN  
clock cycle. This should not be a concern for most applica-  
tions. However, the Timing section contains information on  
exactly synchronizing multiple converters to the same XIN  
clock cycle.  
voltage is 5V and the output format is Offset Binary  
(FFFFFFH). For sink current, the worst-case condition oc-  
curs when the analog input differential voltage is 0V and the  
output format is Two’s Complement (000000H).  
Note that SDOUT is tri-stated for the majority of the  
conversion period and the opto-isolator connection must  
take this into account.  
tDATA  
Synchronization of Multiple Converters  
DRDY A  
The DSYNC input is used to synchronize the output data of  
multiple ADS1212/13s. Synchronization involves configur-  
ing each ADS1212/13 to the same Decimation Ratio and  
Turbo Mode setting, and providing a common signal to the  
XIN inputs. Then, the DSYNC signal is pulsed LOW (see  
Figure 22 in the Timing section). This results in an internal  
reset of the modulator count for the current conversion.  
Thus, all the converters start counting from zero at the same  
time, producing a DRDY LOW signal at approximately the  
same point (see Figure 36).  
tDATA  
DRDY B  
tDATA  
DRDY C  
DSYNC  
tDATA  
FIGURE 36. Effect of Synchronization on Output Data  
Timing.  
ADS1212, 1213  
34  
SBAS064A  
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