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ADS1100IDBVT 参数 Datasheet PDF下载

ADS1100IDBVT图片预览
型号: ADS1100IDBVT
PDF下载: 下载PDF文件 查看货源
内容描述: 自校准, 16位模拟数字转换器 [Self-Calibrating, 16-Bit ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器光电二极管
文件页数/大小: 13 页 / 187 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ADS1100 I2C ADDRESS  
cation for details.) The master sends an address in the  
address byte, together with a bit which indicates whether it  
wishes to read from or write to the slave device.  
The ADS1100s I2C address is 1001aaa, where aaa are bits  
set at the factory. The ADS1100 is shipped with aaa set to  
zero, so its address is 1001000.  
Every byte transmitted on the I2C bus, whether it be address  
or data, is acknowledged with an acknowledge bit. When a  
master has finished sending a byte, eight data bits, to a  
slave, it stops driving SDA and waits for the slave to acknowl-  
edge the byte. The slave acknowledges the byte by pulling  
SDA LOW. The master then sends a clock pulse to clock the  
acknowledge bit. Similarly, when a master has finished  
reading a byte, it pulls SDA LOW to acknowledge this to the  
slave. It then sends a clock pulse to clock the bit. (Remember  
that the master always drives the clock line.)  
Contact Texas Instruments for information about the avail-  
ability of other addresses.  
I2C GENERAL CALL  
The ADS1100 responds to General Call Reset, which is an  
address byte of 00H followed by a data byte of 06H. The  
ADS1100 acknowledges both bytes.  
On receiving a General Call Reset, the ADS1100 performs a  
full internal reset, just as though it had been powered off and  
then on. If a conversion is in process, it is interrupted; the  
output register is set to zero; and the configuration register is  
set to its default setting.  
A not-acknowledge is performed by simply leaving SDA  
HIGH during an acknowledge cycle. If a device is not present  
on the bus, and the master attempts to address it, it will  
receive a not-acknowledge because no device is present at  
that address to pull the line LOW.  
The ADS1100 always acknowledges the General Call ad-  
dress byte of 00H, but it does not acknowledge any General  
Call data bytes other than 04H or 06H.  
When a master has finished communicating with a slave, it  
may issue a stop condition. When a stop condition is issued,  
the bus becomes idle again. A master may also issue  
another start condition. When a start condition is issued while  
the bus is active, it is called a repeated start condition.  
I2C DATA RATES  
The I2C bus operates in one of three speed modes: Stan-  
dard, which allows a clock frequency of up to 100kHz; Fast,  
which allows a clock frequency of up to 400kHz; and High-  
A timing diagram for an ADS1100 I2C transaction is shown in  
Figure 1. Table III gives the parameters for this diagram.  
t(LOW)  
tF  
tR  
t(HDSTA)  
SCL  
SDA  
t(SUSTO)  
t(HDSTA)  
t(HIGH) t(SUSTA)  
t(HDDAT)  
t(SUDAT)  
t(BUF)  
P
S
S
P
FIGURE 1. I2C Timing Diagram.  
FAST MODE  
HIGH-SPEED MODE  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
UNITS  
SCLK Operating Frequency  
f(SCLK)  
0.4  
3.4  
MHz  
ns  
Bus Free Time Between STOP and START Condition t(BUF)  
600  
600  
160  
160  
Hold Time After Repeated START Condition.  
After this period, the first clock is generated.  
t(HDSTA)  
ns  
Repeated START Condition Setup Time  
STOP Condition Setup Time  
Data Hold Time  
t(SUSTA)  
t(SUSTO)  
t(HDDAT)  
t(SUDAT)  
t(LOW)  
t(HIGH)  
tF  
600  
600  
0
160  
160  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Data Setup Time  
100  
1300  
600  
10  
SCLK Clock LOW Period  
SCLK Clock HIGH Period  
Clock/Data Fall Time  
160  
60  
300  
300  
160  
160  
Clock/Data Rise Time  
tR  
TABLE III. Timing Diagram Definitions.  
ADS1100  
9
SBAS239  
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