speed mode (also called Hs mode), which allows a clock
frequency of up to 3.4MHz. The ADS1100 is fully compatible
with all three modes.
In continuous conversion mode, the ADS1100 ignores the
value written to ST/BSY.
When read in single conversion mode, ST/BSY indicates
whether the A/D converter is busy taking a conversion. If ST/
BSY is read as 1, the A/D converter is busy, and a conversion
is taking place; if 0, no conversion is taking place, and the
result of the last conversion is available in the output register.
No special action needs to be taken to use the ADS1100 in
Standard or Fast modes, but High-speed mode must be
activated. To activate High-speed mode, send a special
address byte of 00001XXX following the start condition,
where the XXX bits are unique to the Hs-capable master.
This byte is called the Hs master code. (Note that this is
different from normal address bytes: the low bit does not
indicate read/write status.) The ADS1100 will not acknowl-
edge this byte; the I2C specification prohibits acknowledg-
ment of the Hs master code. On receiving a master code, the
ADS1100 will switch on its High-speed mode filters, and will
communicate at up to 3.4MHz. The ADS1100 switches out of
Hs mode with the next stop condition.
In continuous mode, ST/BSY is always read as 1.
Bits 6-5: Reserved
Bits 6 and 5 must be set to zero.
Bit 4: SC
SC controls whether the ADS1100 is in continuous conver-
sion or single conversion mode. When SC is 1, the ADS1100
is in single conversion mode; when SC is 0, the ADS1100 is
in continuous conversion mode. The default setting is 0.
For more information on High-speed mode, consult the I2C
specification.
REGISTERS
Bits 3-2: DR
The ADS1100 has two registers which are accessible via its
I2C port. The output register contains the result of the last
conversion; the configuration register allows you to change
the ADS1100’s operating mode and query the status of the
device.
Bits 3 and 2 control the ADS1100’s data rate, as shown in
Table VI.
DR1
DR0
DATA RATE
0
0
0
1
128SPS
32SPS
16SPS
8SPS(1)
1
1(1)
0
1(1)
OUTPUT REGISTER
The 16-bit output register contains the result of the last
conversion in binary two’s complement format. Following
reset or power-up, the output register is cleared to zero; it
remains zero until the first conversion is completed. There-
fore, if you read the ADS1100 just after reset or power-up,
you will read zero from the output register.
NOTE: (1) Default Setting
TABLE VI. DR Bits.
Bits 1-0: PGA
Bits 1 and 0 control the ADS1100’s gain setting, as shown in
Table VII.
The output register’s format is shown in Table V.
PGA1
PGA0
GAIN
CONFIGURATION REGISTER
0(1)
0(1)
1
1(1)
2
You can use the 8-bit configuration register to control the
ADS1100’s operating mode, data rate, and PGA settings.
The configuration register’s format is shown in Table IV. The
default setting is 8CH.
0
1
0
4
1
1
8
NOTE: (1) Default Setting.
TABLE VII. PGA Bits.
BIT
7
6
0
5
0
4
3
2
1
0
NAME
ST/BSY
SC
DR1 DR0 PGA1 PGA0
READING FROM THE ADS1100
TABLE IV. Configuration Register.
You can read the output register and the contents of the
configuration register from the ADS1100. To do this, address
the ADS1100 for reading, and read three bytes from the
device. The first two bytes are the output register’s contents;
the third byte is the configuration register’s contents.
Bit 7: ST/BSY
The meaning of the ST/BSY bit depends on whether it is
being written to or read from.
You do not always have to read three bytes from the
ADS1100. If you want only the contents of the output regis-
ter, read only two bytes.
In single conversion mode, writing a 1 to the ST/BSY bit
causes a conversion to start, and writing a 0 has no effect.
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TABLE V. Output Register.
10
ADS1100
SBAS239
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