SPECIFICATIONS
ELECTRICAL
At TC = +25°C, 5.12MHz sampling rate, output data latched with the convert command, RS = 50Ω, ±VCC = +15V, +VDD1 = +5V, –VDD2 = –5.2V, and 15-minute warmup
in convection environment, unless otherwise noted.
ADC614JH
TYP
ADC614KH
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
14
14
Bits
INPUTS
Analog
Input Range
Input Impedance
Input Capacitance
Full Scale
–1.25
+1.25
t-20
✽
✽
✽
V
MΩ
pF
1.5
5
✽
✽
Digital
Logic Family
Convert Command
Pulse Width
Start Conversion
t = Conversion Period
10
✽
ns
TRANSFER CHARACTERISTICS
Accuracy
Gain Error
Input Offset
Differential Linearity Error
DC
DC
±0.8
±0.4
1.3
±2
±2
1.5
±0.4
±0.2
0.9
±1
±0.75
1.25
%FSR(1)
%FSR
LSB
f = 100kHz:
100% of All Codes
No Missing Codes
Power Supply Rejection
Guaranteed
±0.03
±0.04
±0.004
±0.01
Guaranteed
∆+VCC = ±5%
∆–VCC = ±5%
∆+VDD1 = ±5%
∆–VDD2 = ±5%
±0.1
±0.1
±0.07
±0.07
✽
✽
✽
✽
✽
✽
✽
✽
%FSR/%
%FSR/%
%FSR/%
%FSR/%
CONVERSION CHARACTERSITICS
Sample Rate
Pipeline Delay
DC
5.12M
✽
✽
Samples/s
LSB
Logic Selectable
1, 2, or 3 Convert Command Periods
DYNAMIC CHARACTERISTICS(1, 2)
Differential Linearity Error
f = 2.3MHz:
1.3
2.0
0.8
1.25
100% of All Codes
Spurious-Free Dynamic
Range (SFDR)
f = 2.3MHz (–0.5dB)
f = 100kHz (–0.5dB)
Two-Tone Intermodulation Distortion(6)
f = 2.2MHz (–6.5dB)
f = 2.3MHz (–6.5dB)
Signal-to-Noise Ratio (SNR)(6)
f = 2.3MHz (–0.5dB)
f = 100kHz (–0.5dB)
SINAD
f
s = 5.12MHz
77
79
80
82
dBFS(3)
dBFS(3)
fs = 5.12MHz
fs = 5.12MHz
–80
–73
–85
–78
dBFS(3)
71
73
73
75
73
74
74
76
dB
dB
f = 2.3MHz (–0.5dB)
f = 100kHz (–0.5dB)
Aperature Delay Time
Aperature Jitter
Analog Input Bandwidth (–3dB)
Small Signal
f
s = 5.12MHz
72
74
–5
3
73
75
✽
dB
dB
ns
–20
40
+20
10
✽
✽
✽
✽
ps rms
–20dB Input
0dB Input
2x Full-Scale Input
60
30
205
✽
✽
✽
✽
✽
MHz
MHz
ns
Full Power
Overload Recovery Time
400
✽
OUTPUTS
Logic Family
Logic Coding
Logic Levels
TTL Compatible
Two’s Complement or Inverted Two’s Complement
Logic Selectable
Logic “LO”
IOL = –3.2mA
Logic “HI”
0
+0.3
+0.5
✽
✽
✽
✽
V
V
+2.4
+3.5
+5.0
✽
✽
IOH = 160µA
EOC Delay Time
Tri-State Enable/Disable Time
Data Out to DV
IOL = –6.4mA,
50% In to 50% Out
See Timing Diagram: Figure 13
37
100
✽
✽
ns
Data Valid Pulse Width
See Timing Diagram: Figure 13
POWER SUPPLY REQUIREMENTS
Supply Voltages: +VCC
Operating
Operating
Operating
+14.25
–14.25
+4.75
+15
–15
+5
–5.2
+60
–60
+305
–550
6.1
+15.75
–15.75
+5.25
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
✽
V
V
V
–VCC
+VDD1
–VDD2
–4.95
–5.46
✽
V
Supply Currents: +ICC
–ICC
+80
–80
+330
–630
✽
mA
mA
mA
mA
W
(4)
+IDD1
–IDD2
(5)
Power Consumption
6.5
✽Same specifications as next grade to the left.
®
2
ADC614
BB [ BURR-BROWN CORPORATION ]
