Internal timing circuits (ECL logic is used internally) supply
all the critical timing signals necessary for proper operation
of the ADC614. Some noncritical timing signals are also
generated in the digital error correction circuitry. Timing
signals are laser-trimmed for both pulse width and delay.
ECL logic is used for its speed, low noise characteristics and
timing delay stability over a wide range of temperatures and
power supply voltages. Basic timing is derived from the
output of a three-stage shift register driven by a synchro-
nized 20MHz oscillator.
A typical test setup for performing high-speed FFT testing
of analog-to-digital converters is shown in Figure 2 and 3.
Highly accurate phase-locked signal sources allow high
resolution FFT measurements to be made without using
window functions. By choosing appropriate signal frequen-
cies and sample rates, an integral number of signal fre-
quency periods can be sampled. As no spectral leakage
results, a “rectangular” window (no window function) can
be used. This was used to generate the typical FFT perfor-
mance curves shown on page 5.
The convert command pulse is differentiated to allow trig-
gering by pulses from as narrow as 10ns to as wide as 80%
duty cycle.
If generators cannot be phase-locked and set to extreme
accuracy, a very low side-lobe window must be applied to
the digital data before executing an FFT. A commonly used
window such as the Hanning window is not appropriate for
testing high performance converters; a minimum four-sample
Blackman-Harris window is strongly recommended.(l) To
assure that the majority of codes are exercised in the ADC614
(14 bits), a 4096-point FFT is taken. If the data storage RAM
is limited, a smaller FFT may be taken if a sufficient number
of samples are averaged (e.g., a l0-sample average of 512-
point FFTs).
The ADC614 timing technique generates a variable width
S/H gate pulse which is determined by the conversion
command pulse period minus a fixed 135ns ADC conver-
sion time. ADC614 conversion rates are therefore possible
somewhat above the 5.12MHz specification but S/H acqui-
sition time is sacrificed and accuracy is rapidly degraded.
The output of the MSB and LSB encoders are read into
separate 8-bit latches. The latched MSB data, along with the
latched LSB data, is then read into a 16-bit latch after the
leading edge of the LSB strobe and before being applied to
the adder, where the actual error correction takes place.
These latches eliminate any critical timing problems that
could result when the converter is operated at the maximum
conversion rate.
DYNAMIC PERFORMANCE DEFINITIONS
1. Spurious Free Dynamic Range:
Largest Harmonic Power (first 9 harmonics)
Full Scale Power
2. Intermodulation Distortion (IMD):
Highest IMD Product Power (to 5th-order)
Sinewave Signal Power
The function of the digital error correction circuitry is to
assemble the 8-bit words from the two flash encoders into a
14-bit output word.
The 16-bit register output is then sent to a 14-bit adder where
the final data output word is created. The MSB data forms
the most significant eight bits of a 14-bit word, with the last
six bits being assigned zeros. In a similar fashion, the LSB
data from the least significant bits forms the other input to
the adder, with the first six bits being assigned zeros. As two
14-bit words are being added, the output of the adder could
exceed 14 bits in range; however, the final data output is
only a 14-bit word, so a means of detecting an overrange is
included to prevent reading erroneous data. The converter
data output is forced to all ones for a full-scale input or
overrange. The data output does not “roll-over” if the con-
verter input exceeds its specified full-scale range of ±l.25V.
3. Signal-to-Noise Ratio (SNR):
Sinewave Signal Power
Noise Power
4. Signal-to-(Noise + Distortion)(2) Ratio (SINAD):
Sinewave Signal Power
Noise + Harmonic Power (first 9 harmonics)
IMD is referenced(3) to the larger of the test signals fl or f2.
Five “bins” either side of peak are used for calculation of
fundamental and harmonic power. The DC frequency bin is
not included in these calculations as it is of little importance
in dynamic signal processing applications.
DISCUSSION OF
APPLICATION TIPS
PERFORMANCE
DYNAMIC PERFORMANCE TESTING
Attention to test set-up details can prevent errors that con-
tribute to poor test results. Important points to remember
when testing high performance converters are:
The ADC614 is a very high performance converter and
careful attention to test techniques is necessary to achieve
accurate results. Spectral analysis by application of a fast
Fourier transform (FFT) to the ADC digital output will
provide data on all important dynamic performance param-
eters: spurious free dynamic range (SFDR), signal-to-noise
ratio (SNR) or the more severe signal-to-noise-and-distor-
tion ratio (SINAD), and intermodulation distortion (IMD).
1. The ADC analog input must not be overdriven. Using a
signal amplitude slightly lower than FSR will allow a
small amount of “headroom” so that noise or DC offset
voltage will not overrange the ADC and “hard limit” on
signal peaks.
®
8
ADC614
BB [ BURR-BROWN CORPORATION ]
