欢迎访问ic37.com |
会员登录 免费注册
发布采购

AZP53 参数 Datasheet PDF下载

AZP53图片预览
型号: AZP53
PDF下载: 下载PDF文件 查看货源
内容描述: 低相位噪声的正弦波LVPECL缓冲器/分频器 [Low Phase Noise Sine Wave to LVPECL Buffer/Divider]
分类和应用:
文件页数/大小: 9 页 / 224 K
品牌: AZM [ ARIZONA MICROTEK, INC ]
 浏览型号AZP53的Datasheet PDF文件第1页浏览型号AZP53的Datasheet PDF文件第2页浏览型号AZP53的Datasheet PDF文件第3页浏览型号AZP53的Datasheet PDF文件第4页浏览型号AZP53的Datasheet PDF文件第6页浏览型号AZP53的Datasheet PDF文件第7页浏览型号AZP53的Datasheet PDF文件第8页浏览型号AZP53的Datasheet PDF文件第9页  
AZP51  
AZP52  
AZP53  
AZP54  
Absolute Maximum Ratings are those values beyond which device life may be impaired.  
Symbol  
Characteristic  
Rating  
Unit  
VDD  
VI  
TA  
Power Supply  
Input Voltage  
Operating Temperature Range  
Storage Temperature Range  
0 to +5.5  
-0.5 to VDD+0.5  
-40 to +85  
Vdc  
Vdc  
°C  
TSTG  
-65 to +150  
°C  
DC Characteristics (VDD = 3.0V to 3.6V unless otherwise specified, TA = -40 to 85 C)  
Symbol  
Characteristic  
Conditions  
Min  
Typ  
Max  
Unit  
-40 C  
25 C  
85 C  
-40 C  
25 C  
85 C  
2.05  
2.05  
2.05  
1.365  
1.430  
1.490  
2.415  
2.480  
2.540  
1.615  
1.680  
1.740  
VOH  
VOL  
Output HIGH Voltage1  
VDD = 3.3V  
V
Output LOW Voltage1  
VDD = 3.3V  
V
Output Leakage Current, Tri-  
state2  
High Level Input Voltage  
IZ  
EN=Disable3  
-10  
2.0  
10  
μA  
V
VIH  
VIL  
EN_SEL4  
DIV_SEL4  
EN  
EN_SEL  
DIV_SEL  
EN  
Low Level Input Voltage  
0.8  
V
RPU  
RPD  
RP  
Pullup Resistor4  
50k  
50k  
50k  
Pulldown Resistor4  
Pullup/Pulldown Resistor5  
D Input to Internal  
VDD/2 Reference  
RBIAS  
IDD  
Bias Resistor  
10k  
Power Supply Current  
22  
35  
mA  
1.  
2.  
3.  
4.  
5.  
Specified with outputs terminated through 50Ω resistors to VDD - 2V or Thevenin equivalent.  
Measured at Q/Q¯ pins.  
See functional tables for Disable state definition.  
AZP53 only.  
See functional operation table for pullup/pulldown mode selection.  
AC Characteristics (VDD = 3.0V to 3.6V, TA = -40 to 85 C)  
Symbol  
tr / tf  
fMAX  
tpd  
Characteristic  
Unit  
Min  
Max  
Output Rise/Fall1  
(20% - 80%)  
0.25  
0.7  
ns  
Maximum Input  
Frequency – Sine wave2  
Propagation Delay1,3,6  
D to Q/Q¯  
650  
3.0  
MHz  
ns  
1.0  
Enable1,4  
ten  
200  
80  
ns  
EN to Q/Q¯  
Disable1,5  
tdis  
ns  
EN to Q/Q¯  
Phase Noise1,3  
10 MHz offset  
dBc/  
Hz  
nP  
-158  
1.  
2.  
3.  
4.  
5.  
6.  
Specified with outputs terminated through 50Ω resistors to VCC - 2V or Thevenin equivalent.  
750 mv p-p sine wave, AC coupled to D input.  
155 MHz 750 mv p-p sine wave input.  
EN asserted (enabled) to Q/Q¯ outputs producing specified VOH & VOL levels.  
EN deasserted (disabled) to Q/Q¯ outputs VOL min.  
Measured from 50% D to 50% Q/Q¯.  
December 2009 * REV - 2  
www.azmicrotek.com  
5