PRELIMINARY
SPECIFICATION
EEPROM
AS8ERLC128K32
Austin Semiconductor, Inc.
SOFTWARE DATA PROTECTION TIMING WAVEFORM (In non-protection mode)
VCC
Normal
active mode
tWC
CE\
WE\
Address
5555
AA
AAAA 5555 5555 AAAA 5555
or
or
2AAA
2AAA
Data (each byte)
55
80
AA
55
20
FUNCTIONAL DESCRIPTION
Automatic Page Write
RDY/Busy\ Signal
Page-mode write feature allows 1 to 128 bytes of data to be RDY/Busy\ signal also allows status of the EEPROM to be
written into the EEPROM in a single write cycle. Following determined. The RDY/Busy\ signal has high impedance ex-
the initial byte cycle, an additional 1 to 128 bytes can be writ-
ten in the same manner. Each additional byte load cycle must
be started within 30µs from the preceding falling edge of WE\
or CE\. When CE\ or WE\ is kept high for 100µs after data input,
the EEPROM enters write mode automatically and the input
data are written into the EEPROM.
cept in write cycle and is lowered to VOL after the first write
signal. At the end of write cycle, the RDY/Busy\ signal changes
state to high impedance.
RES\ Signal
When RES\ is low, the EEPROM cannot be read or pro-
grammed. Therefore, data can be protected by keeping RES\
DATA\ Polling
low when VCC is switched. RES\ should be high during read
and programming because it doesn't provide a latch function.
See timing diagram below.
DATA\ polling allows the status of the EEPROM to be deter-
mined. If EEPROM is set to read mode during the write cycle,
an inversion of the last byte of data to be loaded outputs from
I/O's 7, 15, 23, and 31 to indicate that the EEPROM is per-
forming a write operation.
RES\ Signal Diagram
VCC
Read inhibit
Read inhibit
RES\1
Program inhibit
Program inhibit
Note(s):
1- RES\=TRUE=VL >/=-0.3v </=0.4v
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8ERLC128K32
Rev. 1.9 06/06
10
AUSTIN [ AUSTIN SEMICONDUCTOR ]
