SDRAM
AS4SD8M16
Austin Semiconductor, Inc.
READ with Auto Precharge
CONCURRENT AUTO PRECHARGE
1. Interrupted by a READ (with or without auto precharge); A
READ to bank m will interrupt a READ on bank n, CAS la-
tency later. The PRECHARGE to bank n will begin when the
READ to bank m is registered (Figure 24).
2. Interrupted by a WRITE (with or without auto precharge):A
WRITE to bank m will interrupt a READ on bank n when
registered. DQM should be used two clocks prior to the WRITE
command to prevent bus contention. The PRECHARGE to
bank n will begin when the WRITE to bank m is registered
(Figure 25).
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ASI
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE oc-
curs are defined below.
FIGURE 24: READ With Auto Precharge Interrupted by a READ
FIGURE 25: READ With Auto Precharge Interrupted by a WRITE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD8M16
Rev. 0.5 04/05
20
AUSTIN [ AUSTIN SEMICONDUCTOR ]
