SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
WRITE -- WITHOUT AUTO PRECHARGE1
T0
T1
T2
CL
T3
T4
T5
T6
T7
T8
t
CLK
CKE
t
t
CK
CH
t
t
t
CKS CKH
t
CMS
CMH
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
ACTIVE
WRITE
COMMAND
t
t
CMS
CMH
DQM /
DQML,
DQMH
t
t
t
t
AH
AS
A0-A9,
A11
COLUMN
m2
ROW
ROW
t
AS
AH
ALL BANKS
SINGLE BANK
BANK
ROW
ROW
A10
BA0, BA1
DQ
t
DISABLE AUTO PRECHARGE
AS
AH
BANK
BANK
BANK
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DIN
m
DIN m+2
DIN m+3
DIN m+1
2
t
t
t
RP
RCD
WR
t
RAS
t
RC
Don’t Care
Undefined
TIMING PARAMETERS
-8
-10
-8
-10
SYMBOL*
tCMH
MIN
MAX
MIN
1
MAX
UNITS
ns
SYMBOL* MIN
tAC(3)
MAX
MIN
MAX
UNITS
ns
1
2
6.5
7
tCMS
tDH
tAC(2)
3
ns
ns
ns
ns
ns
ns
ns
ns
9
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
1
1
1
2
1
3
tDS
tAS
2
3
tRAS
tRC
tRCD
tRP
tCH
50
80
20
24
15
80,000
60
90
30
30
15
80,000
3
3.5
3.5
10
15
1
tCL
3
tCK(3)
tCK(2)
tCKH
tCKS
8
12
1
tWR
2
3
* CAS latency indicated in parentheseses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns are required between <DINm+3> and the PRECHARGE command, regardless of frequency.
3. x16: A8, A9 and A11 = “Don’t Care.”
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
44
AUSTIN [ AUSTIN SEMICONDUCTOR ]
