SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
WRITE -- WITH AUTO PRECHARGE1
T2
T5
T8
T0
T1
T3
T4
T6
T7
T9
CLK
CKE
t
CL
t
t
CK
CH
t
t
t
CKS CKH
t
CMS
CMH
ACTIVE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
COMMAND
WRITE
NOP
t
t
CMS
CMH
DQM /
DQML,
DQMH
t
t
t
t
AH
AS
COLUMN
m2
ROW
ROW
A0-A9,
A11
t
AS
AH
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
AS
AH
BANK
BANK
BANK
BA0, BA1
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS DH
DIN
m
DIN m+1
DIN m+3
DIN m+2
DQ
2
t
t
t
RP
RCD
WR
t
RAS
t
RC
Don’t Care
Undefined
TIMING PARAMETERS
-8
-10
-8
-10
MIN
1
MAX
MIN
1
MAX
SYMBOL*
tAH
UNITS
ns
MIN
1
MAX
MIN
MAX
SYMBOL*
tDH
UNITS
1
ns
ns
ns
ns
ns
ns
tAS
2
3
3
3.5
3.5
10
15
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3
tDS
tCH
50
80
20
24
80,000
60
90
30
30
80,000
tRAS
tRC
tRCD
tRP
tCL
3
tCK(3)
tCK(2)
tCKH
tCKS
tCMH
tCMS
8
12
1
1 CLK+
8ns
1 CLK+
8ns
tWR
ns
2
3
1
1
2
3
* CAS latency indicated in parentheseses.
NOTE: 1. For this example, the burst length = 4, i.e., two-clock minimum for tWR
.
2. x16: A8, A9 and A11 = “Don’t Care.”
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD4M16
Rev. 1.5 10/01
45
AUSTIN [ AUSTIN SEMICONDUCTOR ]
