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AS4SD4M16DG-10/XT 参数 Datasheet PDF下载

AS4SD4M16DG-10/XT图片预览
型号: AS4SD4M16DG-10/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 4梅格×16 SDRAM同步动态随机存取存储 [4 Meg x 16 SDRAM Synchronous DRAM Memory]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 50 页 / 1139 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SDRAM  
AS4SD4M16  
Austin Semiconductor, Inc.  
NOTES  
12. Other input signals are allowed to transition no more  
than once in any 30ns period (20ns on -8) and are  
1. All voltages referenced to VSS.  
2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1  
MHz, TA = 25°C; pin under test biased at 1.4V.  
otherwise at valid VIH or VIL levels.  
13. IDD specifications are tested after the device is properly  
initialized.  
3. IDD is dependent on output loading and cycle rates.  
Specified values are obtained with minimum cycle time  
and the outputs open.  
4. Enables on-chip refresh and address counters.  
5. The minimum specifications are used only to indicate  
cycle time at which proper operation over the full  
14. Timing actually specified by tCKS; clock(s) specified as a  
reference only at minimum cycle rate.  
15. Timing actually specified by tWR plus tRP; clock(s)  
specified as a reference only at minimum cycle rate.  
temperature range (-55°C TA +125°C) is ensured.  
6. An initial pause of 100µs is required after power-up,  
followed by two AUTO REFRESH commands, before  
16. Timing actually specified by tWR  
17. Required clocks are specified by JEDEC functionality  
and are not dependent on any timing parameter.  
.
proper device operation is ensured. (VDD and VDDQ must  
18. The ICC current will decrease as the CAS latency is  
reduced. This is due to the fact that the maximum cycle  
rate is slower as the CAS latency is reduced.  
19. Address transitions average one transition every 30ns  
(20ns on -8).  
20. CLK must be toggled a minimum of two times during this  
period.  
21. Based on tCK = 100 MHz for -8 and 66 MHz for -10.  
22. These five parameters vary between speed grades and  
define the differences between the -8 SDRAM speeds:  
-8.  
be powered up simultaneously. VSS and VSSQ must be at  
same potential.) The two AUTO REFRESH command  
wake-ups should be repeated any time the tREF refresh  
requirement is exceeded.  
7. AC characteristics assume tT = 1ns.  
8. In addition to meeting the transition rate specification,  
the clock and CKE must transit between VIH and VIL (or  
between VIL and VIH) in a monotonic manner.  
9. Outputs measured at 1.5V with equivalent load:  
10. tHZ defines the time at which the output achieves the  
23. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse  
open circuit condition; it is not a reference to VOH or  
width 10ns, and the pulse width cannot be greater than  
VOL. The last valid data element will meet tOH before  
going High-Z.  
one third of the cycle rate. VIL undershoot: VIL (MIN) =  
-2V for a pulse width 10ns, and the pulse width cannot  
be greater than one third of the cycle rate.  
11. AC timing and ICC tests have VIL = 0V and VIH = 3V, with  
timing referenced to 1.5V crossover point.  
24. The clock frequency must remain constant during access  
or precharge states (READ, WRITE, including tWR, and  
PRECHARGE commands). CKE may be used to reduce  
the data rate.  
Q
50pF  
25. Auto precharge mode only. The precharge timing budget  
( tRP) begins 8ns after the first clock delay, after the last  
WRITE is executed.  
26. Precharge mode only.  
27. JEDEC and PC100 specify three clocks.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4SD4M16  
Rev. 1.5 10/01  
33  
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