欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS4SD2M32DGX-6XT 参数 Datasheet PDF下载

AS4SD2M32DGX-6XT图片预览
型号: AS4SD2M32DGX-6XT
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32× 4银行( 64 MB) SDRAM同步 [512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM]
分类和应用: 内存集成电路光电二极管动态存储器
文件页数/大小: 52 页 / 1943 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
 浏览型号AS4SD2M32DGX-6XT的Datasheet PDF文件第2页浏览型号AS4SD2M32DGX-6XT的Datasheet PDF文件第3页浏览型号AS4SD2M32DGX-6XT的Datasheet PDF文件第4页浏览型号AS4SD2M32DGX-6XT的Datasheet PDF文件第5页浏览型号AS4SD2M32DGX-6XT的Datasheet PDF文件第7页浏览型号AS4SD2M32DGX-6XT的Datasheet PDF文件第8页浏览型号AS4SD2M32DGX-6XT的Datasheet PDF文件第9页浏览型号AS4SD2M32DGX-6XT的Datasheet PDF文件第10页  
SDRAM  
AS4SD2M32  
Austin Semiconductor, Inc.  
CAS Latency  
The CAS latency is the delay, in clock cycles, between the  
Operating Mode  
The normal operating mode is selected by setting M7 and  
registration of a READ command and the availability of the first M8 to zero; the other combinations of values for M7 and M8  
piece of output data. The latency can be set to two or three are reserved for future use and/or test modes. The programmed  
clocks.  
If a READ command is registered at clock edge n, and the  
burst length applies to both READ and WRITE bursts.  
Test modes are reserved states should not be used  
latency is m clocks, the data will be available by clock edge because unknown operation or incompatibility with future  
n + m. The DQs will start driving as a result of the clock edge versions may result.  
one cycle earlier (n + m - 1), and provided that the relevant  
access times are met, the data will be valid by clock edge n + m. Write Burst Mode  
For example, assuming that the clock cycle time is such that all  
When M9=0, the burst length programmed via M0-M2  
relevant access times are met, if a READ command is registered applies to both READ and WRITE bursts; when M9=1, the  
at T0 and the latency is programmed to two clocks, the DQs will programmed burst length applies to READ bursts, but write  
start driving after T1 and the data will be valid by T2, as shown accesses are single-location (non-burst) accesses.  
in Figure 2. Table 2 below indicates the operating frequencies  
at which each CAS latency setting can be used.  
Reserved states should not be used as unknown  
operation or incompatibility with future versions may result.  
FIGURE 2: CAS Latency  
TABLE 2: CAS Latency  
ALLOWABLE OPERATING  
FREQUENCY (MHz)  
SPEED  
CAS  
LATENCY = 2  
100  
CAS  
LATENCY = 3  
-6  
166  
-7  
100  
100  
143  
133  
-75  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4SD2M32  
Rev. 1.0 1/08  
6
 复制成功!