AS4SD16M72PBG-s/IT.ET,XT
16M x 72, SDR SDRAM, 3.3v Core/ 3.3v IO
AC Electrical Characteristics
-75
-8
-10
Parameter
Symbol
tAC
tAC
tAH
tAS
tCH
tCL
tCK
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
tHZ
tLZ
tOH
tOHn
tRAS
tRC
tRCD
tREF
tREF
tREF
tRFC
rRP
MIN
MAX
5.4
6
MIN
MAX
MIN
MAX
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
Access time from CLK
CL = 3
CL = 2
6
6
7
7
Address Hold
Address SetUp
1
1
1.5
3
3
8
10
1
2
1
2
1
2
3
1.5
2.5
2.5
7.5
10
1
1.5
1
1.5
1
CLK High Level width
CLK Low Level width
Clock Cycle Time
3
CL = 3
CL = 2
10
13
1
2
1
2
1
2
CKE Hold Time
CKE SetUp Time
CS\, RAS\, CAS\, WE\, DQM Hold Time
CS\, RAS\, CAS\, WE\, DQM SetUp Time
Data-In Hold Time
Data-In SetUp Time
Data Out High Impedance Time
1
2
1.5
CL = 3
CL = 2
5.4
6
6
6
7
7
Data-Out Low Impedance Time
Data-Out Hold Time (under load)
Data-Out Hold Time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
REFRESH period (8,192 rows) Industrial
REFRESH period (8,192 rows) Enhanced
REFRESH period (8,192 rows) Extended
AUTO REFRESH period
1
3
1.8
45
70
20
1
3
1.8
50
70
20
1
3
1.8
50
70
20
120000
120000
120000
64
32
24
64
32
24
64
32
24
66
20
20
68
20
20
70
20
20
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition Time
tRRD
tT
0.3
1.2
0.3
1.2
0.3
1.2
WRITE Recovery Time
tWR
1CLK +
7ns
15
1CLK +
7ns
15
1CLK +
7ns
15
ns
ns
Exit SELF REFRESH to ACTIVE command
tXSR
75
80
80
Austin Semiconductor, Inc.
Proprietary Material
ASI Product Marketing
AUSTIN [ AUSTIN SEMICONDUCTOR ]
