Meg
16 Me g FPM DRAM
Austin Semiconductor, Inc.
TEST MODE CYCLE
11
-60
SYMBOL
t
RC
t
RWC
t
RAC
t
CAC
t
AA
t
RAS
t
CAS
t
RSH
t
CSH
t
RAL
t
CWD
t
RWD
t
AWD
t
CPWD
t
PC
t
PRWC
t
RASP
t
CPA
t
OEA
t
OED
t
OEH
PARAMETER
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS\
Access time from CAS\
Access time from column address
RAS\ pulse width
CAS\ pulse width
RAS\ hold time
CAS\ hold time
Column address to RAS\ lead time
CAS\ to W\ delay time
RAS\ to W\ delay time
Column address to W\ delay time
CAS\ precharge to W\ delay time
Fast Page cycle time
Fast Page read-modify-write time
RAS\ pulse width (Fast Page Cycle)
Access time from CAS\ precharge
OE\ access time
OE\ to data delay
OE\ command hold time
20
20
65
20
20
65
35
45
90
60
65
45
90
65
200K
40
20
MIN
115
160
65
20
35
10K
10K
MAX
MIN
-70
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
7
7
7
3, 4, 10, 12
3, 4, 5, 12
3, 10 ,12
NOTES
AS4LC4M4
NOTES:
1. An initial pause of 200us is required after power-up followed by an 8 RAS\-only refresh or CAS\-before-RAS\ refresh cycles before proper device operation is achieved.
2. V
IH
(MIN) and V
IL
(MAX) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
(MIN) and V
IL
(MAX) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the t
RCD
(MAX) limit insures that t
RAC
(MAX) and be met. t
RCD
(MAX) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(MAX) limit, then access time is
controlled exclusively by t
CAC
.
5. Assumes that t
RCD
> t
RCD
(MAX).
6. t
OFF
(MIN) and t
OEZ
(MAX) define the time at which the output achieves the open circuit condition and are not referenced V
OH
or V
OL
.
7. t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t
WCS
> t
WCS
(MIN), the cycle is an early write cycle and the data
output will remain high impedance for the duration of the cycle. If t
CWD
> t
CWD
(MIN), t
RWD
> t
RWD
(MIN) and t
AWD
> t
AWD
(MIN), then the cycle is a read-modify-write cycle and the data output will
contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.
8. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write cycles.
10. Operation within the t
RAD
(MAX) limit insures that t
RAC
(MAX) can be met. t
RAD
(MAX) is specified as a reference point only. If t
RAD
is greater than the specified t
RAS
(MAX) limit, then access time is
controlled by t
AA
.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of t
RAC
, t
AA
, t
CAC
is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified
value in this data sheet.
13. If t
RASS
> 100 us, then RAS\ precharge time must use t
RPS
instead of t
RP
.
14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within 32ms before and after self refresh, in order to meet refresh specification.
15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
AS4LC4M4
Rev. 0.3 7/06
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
AUSTIN [ AUSTIN SEMICONDUCTOR ]
