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AS4DDR264M64PBG1R-38/ET 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/ET图片预览
型号: AS4DDR264M64PBG1R-38/ET
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
OUTPUT ENABLE/DISABLE  
DLL ENABLE/DISABLE  
The OUTPUT ENABLE function is defined by bit E12, as  
shown in Figure 7. When enabled (E12 = 0), all outputs  
(DQs, DQS, DQS#, RDQS, RDQS#) function normally. When  
disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS,  
DQS#, RDQS, RDQS#) are disabled, thus removing output  
buffer current. The output disable feature is intended to be  
used during ICC characterization of read current.  
The DLL may be enabled or disabled by programming bit  
E0 during the LM command, as shown in Figure 7. The DLL  
must be enabled for normal operation. DLL enable is  
required during power-up initialization and upon returning  
to normal operation after having disabled the DLL for the  
purpose of debugging or evaluation. Enabling the DLL should  
always be followed by resetting the DLL using an LM  
command.  
ON-DIE TERMINATION (ODT)  
The DLL is automatically disabled when entering SELF  
REFRESH operation and is automatically re-enabled and  
reset upon exit of SELF REFRESH operation. Any time the  
DLL is enabled (and subsequently reset), 200 clock cycles  
must occur before a READ command can be issued, to  
allow time for the internal clock to synchronize with the  
external clock. Failing to wait for synchronization to occur  
ODT effective resistance, RTT (EFF), is defined by bits E2  
and E6 of the EMR, as shown in Figure 7. The ODT feature is  
designed to improve signal integrity of the memory channel  
by allowing the DDR2 SDRAM controller to independently  
turn on/off ODT for any or all devices. RTT effective resistance  
values of 50Ω, 75Ω, and 150Ω are selectable and apply to  
each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#, LDQS/  
LDQS#, DM, and UDM/ LDM signals. Bits (E6, E2) determine  
what ODT resistance is enabled by turning on/off “sw1,”  
“sw2,” or “sw3.” The ODT effective resistance value is elected  
by enabling switch “sw1,” which enables all R1 values that  
are 150Ω each, enabling an effective resistance of 75Ω  
(RTT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2 values  
that are 300Ω each, enable an effective ODT resistance of  
150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables R1 values  
of 100Ω enabling effective resistance of 50Ω Reserved  
states should not be used, as unknown operation or  
incompatibility with future versions may result.  
t
t
may result in a violation of the AC or DQSCK parameters.  
OUTPUT DRIVE STRENGTH  
The output drive strength is defined by bit E1, as shown in  
Figure 7. The normal drive strength for all outputs are  
specified to be SSTL_18. Programming bit E1 = 0 selects  
normal (full strength) drive strength for all outputs. Selecting  
a reduced drive strength option (E1 = 1) will reduce all outputs  
to approximately 45-60 percent of the SSTL_18 drive strength.  
This option is intended for the support of lighter load and/or  
point-to-point environments.  
The ODT control ball is used to determine when RTT(EFF)  
is turned on and off, assuming ODT has been enabled via  
bits E2 and E6 of the EMR. The ODT feature and ODT input  
ball are only used during active, active power-down (both  
fast-exit and slow-exit modes), and precharge powerdown  
modes of operation. ODT must be turned off prior to entering  
self refresh. During power-up and initialization of the DDR2  
SDRAM, ODT should be disabled until issuing the EMR  
command to enable the ODT feature, at which point the ODT  
ball will determine the RTT(EFF) value. Any time the EMR  
enables the ODT function, ODT may not be driven HIGH until  
eight clocks after the EMR has been enabled. See “ODT  
Timing” section for ODT timing diagrams.  
DQS# ENABLE/DISABLE  
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is  
the complement of the differential data strobe pair DQS/  
DQS#. When disabled (E10 = 1), DQS is used in a single  
ended mode and the DQS# ball is disabled. When disabled,  
DQS# should be left floating. This function is also used to  
enable/disable RDQS#. If RDQS is enabled (E11 = 1) and  
DQS# is enabled (E10 = 0), then both DQS# and RDQS# will  
be enabled.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
11  
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