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AS4DDR264M64PBG1R-38/ET 参数 Datasheet PDF下载

AS4DDR264M64PBG1R-38/ET图片预览
型号: AS4DDR264M64PBG1R-38/ET
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mx64 DDR2 SDRAM W /共享控制总线集成塑封微电路 [64Mx64 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 28 页 / 243 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
4.2 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M64PBG1  
EXTENDED MODE REGISTER (EMR)  
until it is programmed again or the device loses power.  
Reprogramming the EMR will not alter the contents of the  
memory array, provided it is performed correctly.  
The extended mode register controls functions beyond  
those controlled by the mode register; these additional  
functions are DLL enable/disable, output drive strength, on  
die termination (ODT) (RTT), posted AL, off-chip driver  
impedance calibration (OCD), DQS# enable/disable,  
RDQS/RDQS# enable/disable, and output disable/enable.  
These functions are controlled via the bits shown in Figure  
7. The EMR is programmed via the LOAD MODE (LM)  
command and will retain the stored information  
The EMR must be loaded when all banks are idle and no bursts  
are in progress, and the controller must wait the specified time  
tMRD before initiating any subsequent operation. Violating either  
of these requirements could esult in unspecified operation.  
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION  
1
3
2
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
Address bus  
Extended mode  
register (Ex)  
16 15 14  
n
12 11 10  
Out  
9
8
7
6
5
4
3
2
1
0
2
0
MRS  
RTT  
Posted CAS#  
0
OCD Program  
R
TT ODS DLL  
RDQS DQS#  
Outputs  
Enabled  
Disabled  
E0  
0
DLL Enable  
Enable (normal)  
Disable (test/debug)  
E12  
0
E6 E2 RTT (Nominal)  
1
1
0
0
1
1
0
1
0
1
RTT disabled  
75:  
150:  
50:  
E11 RDQS Enable  
E1 Output Drive Strength  
0
1
No  
(100%)  
0
1
Full  
Reduced  
Yes  
(40-60%)  
Posted CAS# Additive Latency (AL)4  
E10 DQS# Enable  
E5 E4 E3  
0
1
Enable  
Disable  
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
E9 E8 E7 OCD Operation  
3
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD exit  
Reserved  
Reserved  
Reserved  
4
5
6
Reserved  
Enable OCD defaults  
Mode Register Set  
Mode register (MR)  
E15 E14  
0
1
0
1
0
0
1
1
Extended mode register (EMR)  
Extended mode register (EMR2)  
Extended mode register (EMR3)  
Notes:  
1.During initialization, all three bits must be set to “1” for OCD default state, then must be set to “0” before  
initialization is finished, as detailed in the initialization procedure.  
2.E13 (A13) must be programmed to “0” and is reserved for future use.  
3.E16 must be programmed to “0” and is reserved for future use.  
4.Not all AL options are supported in any individual speed grade.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M64PBG1  
Rev. 0.5 06/08  
10  
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