iPEM
1.2 Gb SDRAM-DDR
AS4DDR16M72PBG
Austin Semiconductor, Inc.
TRUTH TABLE - COMMANDS (NOTE 1)
NAME (FUNCTION)
CS#
H
L
RAS#
CAS#
WE#
X
ADDR
X
DESELECT (NOP)(9)
X
H
L
X
H
H
L
NO OPERATION (NOP) (9)
H
X
ACTIVE (Select bank and activate row) (3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
L
H
Bank/Row
Bank/Col
Bank/Col
X
L
H
H
H
L
H
L
L
L
L
H
H
L
L
PRECHARGE (Deactivate row in bank or banks) (5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6,7)
LOAD MODE REGISTER (2)
L
L
Code
X
L
L
H
L
L
L
L
Op-Code
TRUTH TABLE - DM OPERATION
NAME (FUNCTION)
WRITE ENABLE (10)
WRITE INHIBIT (10)
DM
L
DQs
Valid
X
H
N O T E S :
1 . CKE is HIGH for all commands shown except SELF REFRESH.
2 . A0-12 define the op-code to be written to the selected Mode Register.
BA0, BA1 select either the mode register (0, 0) or the extended mode
register (1, 0).
6 . This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if
CKE is LOW.
7 . Internal refresh counter controls row addressing; all inputs and I/Os are
“Don’t Care” except for CKE.
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-8 provide column address; A10 HIGH enables the auto precharge
feature (non-persistent), while A10 LOW disables the auto precharge
feature; BA0, BA1 provide bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH:
All banks precharged and BA0, BA1 are “Don’t Care.”
8. Applies only to read bursts with auto precharge disabled; this command
is undefined (and should not be used) for READ bursts with auto
precharge enabled and for WRITE bursts.
9 . DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding
data.
READ
PRECHARGE
The READ cꢀmmand is ꢁsed tꢀ initiate a bꢁrst read access
tꢀ an active rꢀo. The valꢁe ꢀn the BA0, BA1 inpꢁts selects
the bank, and the address prꢀvided ꢀn inpꢁts A0-8 selects
the starting cꢀlꢁmn lꢀcatiꢀn. The valꢁe ꢀn inpꢁt A10
determines ohether ꢀr nꢀt AUTO PRECHARGE is ꢁsed. If
AUTO PRECHARGE is selected, the rꢀo being accessed
oill be precharged at the end ꢀf the READ bꢁrst; if AUTO
PRECHARGE is nꢀt selected, the rꢀo oill remain ꢀpen fꢀr
sꢁbseqꢁent accesses.
The PRECHARGE cꢀmmand is ꢁsed tꢀ deactivate the ꢀpen
rꢀo in a particꢁlar bank ꢀr the ꢀpen rꢀo in all banks. The
bank(s) oill be available fꢀr a sꢁbseqꢁent rꢀo access a
specified time (tRP) after the PRECHARGE cꢀmmand is
issꢁed. Except in the case ꢀf cꢀncꢁrrent aꢁtꢀ precharge,
ohere a READ ꢀr WRITE cꢀmmand tꢀ a different bank is
allꢀoed as lꢀng as it dꢀes nꢀt interrꢁpt the data transfer in
the cꢁrrent bank and dꢀes nꢀt viꢀlate any ꢀther timing
parameters. Inpꢁt A10 determines ohether ꢀne ꢀr all banks
are tꢀ be precharged, and in the case ohere ꢀnly ꢀne bank
is tꢀ be precharged, inpꢁts BA0, BA1 select the bank.
Otheroise BA0, BA1 are treated as “Dꢀn’t Care.” Once a
bank has been precharged, it is in the idle state and mꢁst
be activated priꢀr tꢀ any READ ꢀr WRITE cꢀmmands being
issꢁed tꢀ that bank. A PRECHARGE cꢀmmand oill be treated
as a NOP if there is nꢀ ꢀpen rꢀo in that bank (idle state), ꢀr
if the previꢀꢁsly ꢀpen rꢀo is already in the prꢀcess ꢀf
precharging.
WRITE
The WRITE cꢀmmand is ꢁsed tꢀ initiate a bꢁrst orite access
tꢀ an active rꢀo. The valꢁe ꢀn the BA0, BA1 inpꢁts selects
the bank, and the address prꢀvided ꢀn inpꢁts A0-8 selects
the starting cꢀlꢁmn lꢀcatiꢀn. The valꢁe ꢀn inpꢁt A10
determines ohether ꢀr nꢀt AUTO PRECHARGE is ꢁsed. If
AUTO PRECHARGE is selected, the rꢀo being accessed
oill be precharged at the end ꢀf the WRITE bꢁrst; if AUTO
PRECHARGE is nꢀt selected, the rꢀo oill remain ꢀpen fꢀr
sꢁbseqꢁent accesses. Inpꢁt data appearing ꢀn the D/Qs
isoritten tꢀ the memꢀry array sꢁbject tꢀ the DQM inpꢁt lꢀgic
level appearing cꢀincident oith the data. If a given DQM signal
is registered LOW, the cꢀrrespꢀnding data oill be oritten tꢀ
memꢀry; if the DQM signal is registered HIGH, the
cꢀrrespꢀnding data inpꢁts oill be ignꢀred, and a WRITE oill
nꢀt be execꢁted tꢀ that byte/cꢀlꢁmn lꢀcatiꢀn.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4DDR16M72PBG
Rev. 2.1 06/09
9
AUSTIN [ AUSTIN SEMICONDUCTOR ]
