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AS4DDR16M72PBG 参数 Datasheet PDF下载

AS4DDR16M72PBG图片预览
型号: AS4DDR16M72PBG
PDF下载: 下载PDF文件 查看货源
内容描述: 16Mx72 DDR SDRAM集成塑封微电路 [16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 19 页 / 358 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
1.2 Gb SDRAM-DDR  
AS4DDR16M72PBG  
Austin Semiconductor, Inc.  
OPERATING MODE  
FIGURE 1 - MODE REGISTER DEFINITION  
The nꢀrmal ꢀperating mꢀde is selected by issꢁing a MODE  
REGISTER SET cꢀmmand oith bits A7-A12 each set tꢀ zerꢀ,  
and bits A0-A6 set tꢀ the desired valꢁes. A DLL reset is  
initiated by issꢁing a MODE REGISTER SET cꢀmmand oith  
bits A7 andA9-A12 each set tꢀ zerꢀ, bitA8 set tꢀ ꢀne, and bits  
A0-A6 set tꢀ the desired valꢁes. Althꢀꢁgh nꢀt reqꢁired,  
JEDEC specificatiꢀns recꢀmmend ohen a LOAD MODE  
REGISTER cꢀmmand is issꢁed tꢀ reset the DLL, it shꢀꢁld  
aloays be fꢀllꢀoed by a LOAD MODE REGISTER cꢀmmand  
tꢀ select nꢀrmal ꢀperating mꢀde.  
A
10  
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
BA  
1
BA  
0
A12  
A
11  
Address Bus  
Mode Register (Mx)  
0*  
0*  
Operating Mode  
CAS Latency BT  
Burst Length  
*
M14 and M13  
(BA0 and BA1 must be  
"0, 0" to select  
the base mode register  
(vs. the extended  
mode register).  
Burst Length  
M2 M1 M0  
M3 = 0  
M3 = 1  
Reserved  
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved  
2
4
4
All ꢀther cꢀmbinatiꢀns ꢀf valꢁes fꢀr A7-A12 are reserved fꢀr  
fꢁtꢁre ꢁse and/ꢀr test mꢀdes. Test mꢀdes and reserved  
states shꢀꢁld nꢀt be ꢁsed becaꢁse ꢁnknꢀon ꢀperatiꢀn ꢀr  
incꢀmpatibility oith fꢁtꢁre versiꢀns may resꢁlt.  
8
8
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
EXTENDED MODE REGISTER  
Burst Type  
M3  
The extended mꢀde register cꢀntrꢀls fꢁnctiꢀns beyꢀnd thꢀse  
cꢀntrꢀlled by the mꢀde register; these additiꢀnal fꢁnctiꢀns  
are DLL enable/disable, ꢀꢁtpꢁt drive strength, and QFC#.  
These fꢁnctiꢀns are cꢀntrꢀlled via the bits shꢀon in Figꢁre  
3. The extended mꢀde register is prꢀgrammed via the LOAD  
MODE REGISTER cꢀmmand tꢀ the mꢀde register (oith BA0  
= 1 and BA1 = 0) and oill retain the stꢀred infꢀrmatiꢀn ꢁntil it  
is prꢀgrammed again ꢀr the device lꢀses pꢀoer. The  
enabling ꢀf the DLL shꢀꢁld aloays be fꢀllꢀoed by a LOAD  
MODE REGISTER cꢀmmand tꢀ the mꢀde register (BA0/BA1  
bꢀth LOW) tꢀ reset the DLL.  
0
1
Sequential  
Interleaved  
CAS Latency  
M6 M5 M4  
Reserved  
Reserved  
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved  
Reserved  
Reserved  
2.5  
Reserved  
M11  
0
M10  
0
M9  
0
M8  
0
M7  
0
M6-M0  
Valid  
Operating Mode  
M12  
0
Normal Operation  
The extended mꢀde register mꢁst be lꢀaded ohen all banks  
are idle and nꢀ bꢁrsts are in prꢀgress, and the cꢀntrꢀller  
mꢁst oait the specified time befꢀre initiating any sꢁbseqꢁent  
ꢀperatiꢀn. Viꢀlating either ꢀf these reqꢁirements cꢀꢁld resꢁlt  
in ꢁnspecified ꢀperatiꢀn.  
0
0
0
1
0
0
Valid  
Normal Operation/Reset DLL  
-
-
-
All other states reserved  
-
-
-
-
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS4DDR16M72PBG  
Rev. 2.1 06/09  
7
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