iPEM
1.2 Gb SDRAM-DDR
AS4DDR16M72PBG
Austin Semiconductor, Inc.
29. The Inpꢁt capacitance per pin grꢀꢁp oill nꢀt differ by mꢀre than this
maximꢁm amꢀꢁnt fꢀr any given device.
d) The variatiꢀn in driver pꢁll-ꢁp cꢁrrent oithin nꢀminal limits ꢀf vꢀltage
and temperatꢁre is expected, bꢁt nꢀt gꢁaranteed, tꢀ lie oithin the inner
bꢀꢁnding lines ꢀf the V-I cꢁrve ꢀf Figꢁre B.
30. CLK and CLK# inpꢁt sleo rate mꢁst be > 1V/ns (>2V/ns differentially).
31. DQ and DM inpꢁt sleo rates mꢁst nꢀt deviate frꢀm DQS by mꢀre than
10%. If the DQ/DM/DQS sleo rate is less than 0.5V/ns, timing mꢁst be
derated: 50ps mꢁst be added tꢀ tDS and tDH fꢀr each 100mV/ns redꢁctiꢀn
in sleo rate. If sleo rate exceeds 4V/ns, fꢁnctiꢀnality is ꢁncertain.
32. VCC mꢁst nꢀt vary mꢀre than 4% if CKE is nꢀt active ohile any bank is
active.
e) The fꢁll variatiꢀn in the ratiꢀ ꢀf the maximꢁm tꢀ minimꢁm pꢁll-ꢁp
and pꢁll-dꢀon cꢁrrent shꢀꢁld be betoeen .71 and 1.4, fꢀr device drain-
tꢀ-sꢀꢁrce vꢀltages frꢀm 0.1V tꢀ 1.0 Vꢀlt, and at the same vꢀltage and
temperatꢁre.
f) The fꢁll variatiꢀn in the ratiꢀ ꢀf the nꢀminal pꢁll-ꢁp tꢀ pꢁll-dꢀon cꢁrrent
shꢀꢁld be ꢁnity 10%, fꢀr device drain-tꢀ-sꢀꢁrce vꢀltages frꢀm 0.1V
tꢀ 1.0 Vꢀlt.
33. The clꢀck is allꢀoed ꢁp tꢀ 150ps ꢀf jitter. Each timing parameter is
allꢀoed tꢀ vary by the same amꢀꢁnt.
39. The voltage levels used are derived from a minimum VCC level and the
34. tHP min is the lesser ꢀf tCL minimꢁm and tCH minimꢁm actꢁally applied tꢀ
the device CLK and CLK# inpꢁts, cꢀllectively dꢁring bank active.
35. READs and WRITEs oith aꢁtꢀ precharge are nꢀt allꢀoed tꢀ be issꢁed ꢁntil
tRAS(MIN) can be satisfied priꢀr tꢀ the internal precharge cꢀmmand being
issꢁed.
referenced test load. In practice, the voltage levels obtained from
a
properly terminated bus will provide significantly different voltage values.
40. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width < 3ns and the
pulse width can not be greater than 1/3 of the cycle rate.
41. VCC and VCCQ must track each other.
36. Any pꢀsitive glitch mꢁst be less than 1/3 ꢀf the clꢀck and nꢀt mꢀre than
+400mV ꢀr 2.9 vꢀlts, ohichever is less. Any negative glitch mꢁst be less
than 1/3 ꢀf the clꢀck cycle and nꢀt exceed either -300mV ꢀr 2.2 vꢀlts,
ohichever is mꢀre pꢀsitive.
42. This maximum value is derived from the referenced test load. In practice,
the values obtained in
a typical terminated design may reflect up to
310ps less for tHZ(MAX) and the last DVW. tHZ(MAX) will prevail over
tDQSCK(MAX) + tRPST(MAX) condition. tLZ(MIN) will prevail over tDQSCK(MIN)
37. Nꢀrmal Oꢁtpꢁt Drive Cꢁrves:
+
tRPRE(MAX) condition.
a) The fꢁll variatiꢀn in driver pꢁll-dꢀon cꢁrrent frꢀm minimꢁm tꢀ maximꢁm
prꢀcess, temperatꢁre and vꢀltage oill lie oithin the ꢀꢁter bꢀꢁnding lines
ꢀf the V-I cꢁrve ꢀf Figꢁre A.
b) The variatiꢀn in driver pꢁll-dꢀon cꢁrrent oithin nꢀminal limits ꢀf vꢀltage
and temperatꢁre is expected, bꢁt nꢀt gꢁaranteed, tꢀ lie oithin the inner
bꢀꢁnding lines ꢀf the V-I cꢁrve ꢀf Figꢁre A.
43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps
earlier.
44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC
+ 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even
if VCC/VCCQ are
0 volts, provided a minimum of 42 ohms of series
resistance is used between the VTT supply and the input pin.
c) The fꢁll variatiꢀn in driver pꢁll-ꢁp cꢁrrent frꢀm minimꢁm tꢀ maximꢁm
prꢀcess, temperatꢁre and vꢀltage oill lie oithin the ꢀꢁter bꢀꢁnding lines
ꢀf the V-I cꢁrve ꢀf Figꢁre B.
45. The current part operates below the slowest JEDEC operating frequency
of 83 MHz.
As such, future die may not reflect this option.
46. Reserved for future use.
d) The variatiꢀn in driver pꢁll-ꢁp cꢁrrent oithin nꢀminal limits ꢀf vꢀltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up
and pull-down current should be between .71 and 1.4, for device drain-
to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and
temperature.
47. Reserved for future use.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is
executed. That is, from the time the AUTO REFRESH command is
registered, CKE must be active at each rising clock edge, until tRFC has
been satisfied.
f) The full variation in the ratio of the nominal pull-up to pull-down current
should be unity ¡À10%, for device drain-to-source voltages from 0.1V
to 1.0 Volt.
51. ICC2N specifies the DQ, DQS, and DM to be driven to a valid high or low
logic level. ICC2Q is similar to ICC2F except ICC2Q specifies the address
and control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are
similar, ICC2F is “worst case.”
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines
of the V-I curve of Figure C.
52. Whenever the operating frequency is altered, not including jitter, the DLL
is required to be reset. This is followed by 200 clock cycles before any
READ command.
b) The variation in driver pull-down current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines
of the V-I curve of Figure D.
53. VTT is not applied directly to the device; however, tVTD should be greater
than or equal to zero to avoid device latch-up. VCCQ, VTT and VREF must
be equal to or less than VCC + 0.3V. Alternatively VTT may be 1.35V max
during power-up even if VCC/VCCQ are 0V, provided a minimum of 42 &! of
series resistance is used between the VTT supply and the input pin. Once
initialized, VREF must always be powered within the specified range.
FIGURE C - PULL-DOWN CHARACTERISTICS
FIGURE D - PULL-UP CHARACTERISTICS
0
80
Maximum
-10
70
Minimum
-20
-30
-40
-50
-60
-70
-80
60
Nominal high
50
Nominal low
40
Nominal low
30
Minimum
Nominal high
Maximum
20
10
0
0.0
0.5
1.0
CCQ -
1.5
VOUT (V)
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
V
VOUT (V)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4DDR16M72PBG
Rev. 2.1 06/09
16
AUSTIN [ AUSTIN SEMICONDUCTOR ]
