iPEM
1.2 Gb SDRAM-DDR
AS4DDR16M72PBG
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING
CHARACTERISTICS (NOTES 1-5, 14-17, 33)
-8, 250 [200] Mbps
@CL=2.5 [CL=2]
-10, 200 [167] Mbps
@CL=2.5 [CL=2]
Parameter
Access window of DQs from CLK/CLK#
Symbol
tAC
Min
-0.8
0.45
0.45
8
Max
+0.8
0.55
0.55
13
Min
-0.8
0.45
0.45
10
Max
+0.8
0.55
0.55
13
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
µs
µs
µs
ns
ns
tCK
CLK high-level width (30)
CLK low-level width (30)
tCH
tCL
CL=2.5 (45, 52)
CL=2 (45, 52)
t
CK (2.5)
tCK (2)
tDH
Clock cycle time
10
13
13
15
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26,31)
DQ and DM input pulse with (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
0.6
0.6
2
0.6
tDS
0.6
tDIPW
tDQSCK
2
-0.8
0.35
0.35
+0.8
-0.8
0.35
0.35
+0.8
tDQSH
DQS input high pulse width
tDQSL
DQS-DQ skew, DQS to last valid, per group, per access (25,26)
Write command to first DQS latching transition
DQS falling edge to CLK rising - setup time
DQS falling edge to CLK rising - hold time
Half clock period (34)
tDQSQ
tDQSS
tDSS
tDSH
tHP
0.6
0.6
0.75
0.2
1.25
0.75
0.2
1.25
0.2
0.2
tCH, tCL
tCH, tCL
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 43)
Address and control input hold time (fast slew rate) (14)
Address and control input setup time (fast slew rate) (14)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
tHZ
+0.8
+0.8
tLZ
-0.8
1.1
1.1
1.1
1.1
16
-0.8
1.1
1.1
1.1
1.1
16
tIHF
tISF
tIHS
tISS
tMRD
tQH
tHP-tQHS
tHP-tQHS
tQHS
tRAS
tRAP
tRC
1
1
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (50)
ACTIVE to READ or WRITE delay
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
tRFC
tRCD
tRP
PRECHARGE command period
DQS read preamble (42)
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
1.1
0.6
1.1
0.6
DQS read postamble
Active bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20,21)
DQS write postamble (19)
0.4
15
1
0.6
0.4
15
1
0.6
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
tWTR
NA
tQH-tDQSQ
tQH-tDQSQ
REFRESH to REFRESH command interval (Commercial & Industrial temp tREFC
70.3
35
70.3
35
REFRESH to REFRESH command interval (Military temp only) (23)
Average periodic refresh interval (Commercial & Industrial temp only) (23)
Average periodic refresh interval (Military temp only) (23)
Terminating voltage delay to Vcc (53)
tREFC
tREFI
tREFI
tVTD
7.8
3.9
7.8
3.9
0
0
Exit SELF REFRESH to non-READ command
tXSNR
tXSRD
80
80
Exit SELF REFRESH to READ command
200
200
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4DDR16M72PBG
Rev. 2.1 06/09
14
AUSTIN [ AUSTIN SEMICONDUCTOR ]
