FLASH
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toggle. (The system may use either OE\ or CE\ to control the
read cycles.) When the operation is complete, DQ6 stops
toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for
approximately 100µs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
Reading Toggle Bit DQ6/DQ2
Refer to Figure 4 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read DQ7-DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has
FIGURE 4: TOGGLE BIT ALGORITHM
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the device
enters the Erase Suspend mode, DQ6 stops toggling. However
the system must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data\ Polling”).
If a program address falls within a protected sector, DQ6
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the “AC
Characteristics” section for the timing diagram. The DQ2 vs.
DQ6 figure shows the differences between DQ2 and DQ6 in
graphical form. See also the subsection on “DQ2: Toggle
Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that sec-
tor is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE\ pulse in the command sequence.
DQ2 toggles when the system reads at addresses within
those sectors taht have been selected for erasure. (The system
may use either OE\ or CE\ to control the read cycles.) But DQ2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer
to Table 5 to compare outputs for DQ2 and DQ6.
Figure 4 shows the toggle bit algorithm in flowchart form,
and the section “DQ2: Toggle Bit II” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle NOTE:
1) Read toggle bit twice to determine whether or not it is toggling. See
text.
2) Recheck toggle bit because it may stop toggling as DQ5 changes to
“1”. See text.
Bit Timings figure for the toggle bit timing diagram. The DQ2
vs. DQ6 figure shows the differences between DQ2 and DQ6 in
graphical form.
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