FLASH
AS29F040
Austin Semiconductor, Inc.
FIGURE 7: TEST CONDITIONS,
Test Setup
TABLE 6: TEST CONDITIONS,
Test Specifications
CONDITIONS
Output Load
-55
ALL OTHERS UNIT
1 TTL Gate
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
Input Rise and Fall Times
Input Pulse Levels
5
20
ns
V
0ꢀ0 - 3ꢀ0
0ꢀ45 - 2ꢀ4
Input timing measurement
reference levels
Output timing measurement
reference levels
1ꢀ5
1ꢀ5
0ꢀ8, 2ꢀ0
0ꢀ8, 2ꢀ0
V
V
AC CHARACTERISTICS: Read-Only Operations
1
SPEED OPTIONS
SYMBOL
PARAMETER
JEDEC Std
TEST SETUP
MIN
-55
-70
90
-120 -150 UNITS
3
t
t
55
70
90
120 150
120 150
120 150
ns
Read Cycle Time
AVAV
RC
CE\ = V
IL
Address to Output Delay
t
t
MAX
55
70
90
ns
AVQV
ACC
OE\ = V
IL
IL
Chip Enable to Output Delay
Output Enable to Output Delay
t
t
OE\ = V
MAX
MAX
MAX
55
30
18
18
0
70
30
20
20
0
90
35
20
20
0
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
CE
t
t
t
t
50
30
30
0
55
35
35
0
OE
2, 3
t
t
Chip Enable to Output High Z
DF
2, 3
Output Enable to Output High Z
GHQZ
DF
Read
MIN
MIN
3
t
Output Enable Hold Time
OEH
Toggle and
Data Polling
10
0
10
0
10
0
10
0
10
0
ns
ns
Output Hold Time From Addresses
CE\ or OE\, Whichever Occurs First
t
t
MIN
AXQX
OH
NOTES:
1. See Figure 7 and Table 6 for test specifications.
2. Output driver disable time.
3. Not 100% tested.
AS29F040
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 2.2 09/07
15
AUSTIN [ AUSTIN SEMICONDUCTOR ]
