PEM
Austin Semiconductor, Inc.
Functional Block Diagram:
Input
Buffer
I/O
CNTL
Logic
ADDR
Buffer/
Latch
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
128KB Memory Block (3)
X
Decode
ADDR.
Counter
Block
Erase
Control
WRITE
Buffer
AS28F128J3M
Q-Flash
Power
(Current)
Control
Bus
Configuration
Register [BCR]
CEx
OE\
WE\
RP\
WP\
CLK
STS
VPEN
WAIT
VPP
Switch
Pump
Sense Amplifiers
WRITE/ERASE Bit
Compare and
Verify
Command
Execution
Logic
[CEL]
128KB Memory Block (n)
DQ0-8 or
DQ0-15
Y
Dec.
Y - Select
Control
ISM
Status
Register
Identification
Register
Query
Output
Buffer
Additionally, the Scaleable Command Set [SCS] allows a single,
simple software driver in all host systems to work with all SCS
compliant FLASH memory devices. The SCS provides the fastest
system/device data transfer rates and minimizes the device and
system-level implementation costs.
To optimize the processor-memory interface, the device
accommodates VPEN, which is switchable during BLOCK
ERASE, PROGRAM, or LOCK BIT configurations and in
addition can be hard-wired to VCC all dependent on the end
application(s). VPEN is treated as an input pin to enable
ERASING, PROGRAMMING, and BLOCK LOCKING. When
VPEN is lower than the VCC lockout voltage (VLKO), all
program functions are disabled. BLOCK ERASE SUSPEND
mode enables the user to stop BLOCK ERASE to READ data
from or PROGRAM data to any other blocks. Similarly,
PROGRAM SUSPEND mode enables the user to SUSPEND
PROGRAMMING to READ data or execute code from any un-
suspended block(s).
AS28F128J3MRG
Revision 5.0 11/23/04
VPEN serves as an input with 2.7V, 3.3V or 5V levels for
application programming. VPEN in this Q-Flash device can
provide data protection when connected to ground. This pin also
enables PROGRAM or ERASE LOCKOUT functions/controls
during power transitions.
This device is an even-sectored device architecture offering
individual BLOCK LOCKING that can LOCK and UN-LOCK a
block using the SECTOR LOCK BITS command sequence.
Status [STS] is a logic signal output that gives an additional
indicator of the internal state machine [ISM] activity by providing
a hardware signal of both the status and status masking. This
status indicator minimizes central processing unit overhead and
system power consumption. In the default mode, STS acts as an
RY/BY\ pin. When LOW, STS indicates that the ISM is
performing a BLOCK ERASE, PROGRAM, or LOCK BIT
configuration. When HIGH, STS indicates that the ISM is ready
for a new command.
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at
www.austinsemiconductor.com
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