ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
conversion. The data outputs are always enabled and data can
be latched with the BUSY\ rising edge. Mode 1a shows
operation with a narrow logic low CONVST\ pulse. Mode 1b
shows a narrow logic high CONVST\ pulse.
In mode 2 (Figure 18), CS\ is tied low. The falling edge of
the CONVST\ signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD\ signal.
Mode 2 can be used for operation with a shared MPU databus.
In slow memory and ROM modes (Figures 19 and 20), CS\
is tied low and CONVST\ and RD\ are tied together. The MPU
starts the conversion and reads the output with the RD\ signal.
Conversions are started by the MPU or DSP (no external sample
clock).
In slow memory mode, the processor applies a logic low
to RD\ (= CONVST\), starting the conversion. BUSY\ goes low,
forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results appear on
the data outputs; BUSY\ goes high, releasing the processor
and the processor takes RD\ (= CONVST\) back high and reads
the new conversion data.
In ROM mode, the processor takes RD\ (= CONVST\) low,
starting a conversion and reading the previous conversion
result.After the conversion is complete, the processor can read
the new result and initiate another conversion.
Power Shutdown
The AS1419 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap mode
reduces the power by 95% and leaves only the digital logic and
reference powered up. The wake-up time from nap to active is
400ns. In sleep mode, the reference is shut down and only a
small current remains, about 250μA. Wake-up time from sleep
mode is much slower since the reference circuit must power up
and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-
up time is dependent on the value of the capacitor connected
to the REFCOMP (Pin 4). The wake-up time is 10ms with the
recommended 10μF capacitor. Shutdown is controlled by Pin 21
(SHDN\); the ADC is in shutdown when it is low. The shut-
down mode is selected with Pin 20 (CS\); low selects nap.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST\, CS\ and RD\. A logic “0”
applied to the CONVST\ pin will start a conversion after the
ADC has been selected (i.e., CS\ is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY\ output. BUSY\ is
low during a conversion.
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 17), CS\ and RD\
are both tied low. The falling edge of CONVST\ starts the
FIGURE 14a: CS\ to SHDN\ Timing
FIGURE 14a: SHDN\ to CONVST\
Wake-Up Timing
FIGURE 15: CS\ to CONVST\
Set-Up Timing
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 1.5 08/09
14
AUSTIN [ AUSTIN SEMICONDUCTOR ]
