ADC
AS1419
AS1419A
Austin Semiconductor, Inc.
100Ω source resistor to limit the input bandwidth to 1.6MHz.
The 1000pF capacitor also acts as a charge reservoir for the
input sample-and-hold and isolates the ADC input from
sampling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can also
generate distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors are
much less susceptible to both problems.
Input Range
The 2.5V input range of theAS1419 is optimized for low
noise and low distortion. Most op amps also perform well over
this same range, allowing direct coupling to the analog inputs
and eliminating the need for special translation circuitry.
Some applications may require other input ranges. The
AS1419 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
FIGURE 8a: AS1419 Reference Circuit
Internal Reference
The AS1419 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory trimmed
to 2.500V. It is connected internally to a reference amplifier and
is available at VREF (Pin 3) see Figure 8a.A2k resistor is in series FIGURE 8b: Using an External Reference
with the output so that it can be easily overdriven by an exter-
nal reference or other circuitry, see Figure 8b. The reference
amplifier gains the voltage at the VREF pin by 1.625 to create the
required internal reference voltage. This provides buffering
between the VREF pin and the high speed capacitive DAC. The
reference amplifier compensation pin (REFCOMP, Pin 4) must
be bypassed with a capacitor to ground. The reference
amplifier is stable with capacitors of 1µF or greater. For the best
noise performance, a 10µF ceramic or 10µF tantalum in parallel
with a 0.1µF ceramic is recommended.
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the peak
input signal amplitude may vary. The input span of the ADC
can then be adjusted to match the peak input signal, maximizing
the signal-to-noise ratio. The filtering of the internal AS1419
FIGURE 9: Driving VREF with a DAC
reference amplifier will limit the bandwidth and settling time of
this circuit.Asettling time of 5ms should be allowed for after a
reference adjustment.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS1419 & AS1419A
Rev. 1.5 08/09
11
AUSTIN [ AUSTIN SEMICONDUCTOR ]
