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AS1419F-XT 参数 Datasheet PDF下载

AS1419F-XT图片预览
型号: AS1419F-XT
PDF下载: 下载PDF文件 查看货源
内容描述: 14位, 800ksps的采样A / D转换器,带有关断 [14 Bit, 800ksps Sampling A/D Converter with Shutdown]
分类和应用: 转换器
文件页数/大小: 20 页 / 998 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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ADC  
AS1419  
AS1419A  
Austin Semiconductor, Inc.  
BOARD LAYOUT AND GROUNDING  
leads to +AIN (Pin 1) and –AIN (Pin 2) should be kept as short as  
possible. In applications where this is not possible, the +AIN  
and –AIN traces should be run side by side to equalize  
coupling.  
Wire wrap boards are not recommended for high  
resolution or high speed A/D converters. To obtain the best  
performance from theAS1419, a printed circuit board with ground  
plane is required. Layout should ensure that digital and analog  
signal lines are separated as much as possible. Particular care  
should be taken not to run any digital track alongside an  
analog signal track or underneath the ADC.The analog input  
should be screened by AGND.  
SUPPLY BYPASSING  
High quality, low series resistance ceramic, 10µF bypass  
capacitors should be used at the VDD and REFCOMP pins.  
Surface mount ceramic capacitors provide excellent bypassing  
in a small board space.Alternatively, 10µF tantalum capacitors  
in parallel with 0.1µF ceramic capacitors can be used. Bypass  
capacitors must be located as close to the pins as possible.  
The traces connecting the pins and the bypass capacitors must  
An analog ground plane separate from the logic system  
ground should be established under and around the ADC. Pin  
5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all other  
analog grounds should be connected to this single analog  
ground point. The REFCOMP bypass capacitor and the DVDD  
bypass capacitor should also be connected to this analog be kept short and should be made as wide as possible.  
ground plane. No other digital grounds should be connected  
to this analog ground plane. Low impedance analog and digital  
DIGITAL INTERFACE  
power supply common returns are essential to low noise  
operation of theADC and the foil width for these tracks should  
be as wide as possible. In applications where the ADC data  
outputs and control signals are connected to a continuously  
active microprocessor bus, it is possible to get errors in the  
conversion results. These errors are due to feedthrough from  
the microprocessor to the successive approximation  
comparator. The problem can be eliminated by forcing the  
microprocessor into a WAIT state during conversion or by  
using three-state buffers to isolate theADC data bus. The traces  
connecting the pins and bypass capacitors must be kept short  
and should be made as wide as possible.  
The A/D converter is designed to interface with  
microprocessors as a memory mapped device. The CS\ and RD\  
control inputs are common to all peripheral memory interfacing.  
A separate CONVST\ is used to initiate a conversion.  
Internal Clock  
TheA/D converter has an internal clock that eliminates the  
need of synchronization between the external clock and the CS\  
and RD\ signals found in other ADCs. The internal clock is  
factory trimmed to achieve a typical conversion time of 0.95μs  
and a maximum conversion time over the full operating  
temperature range of 1.15μs. No external adjustments are  
required. The guaranteed maximum acquisition time is 300ns. In  
addition, a throughput time of 1.25μs and a minimum sampling  
rate of 800ksps are guaranteed.  
The AS1419 has differential inputs to minimize noise  
coupling. Common mode noise on the +AIN and –AIN leads will  
be rejected by the input CMRR. The –AIN input can be used as  
a ground sense for the +AIN input; the AS1419 will hold and  
convert the difference voltage between +AIN and –AIN. The  
FIGURE 12: Power Supply Grounding Practice  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS1419 & AS1419A  
Rev. 1.5 08/09  
13  
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