AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
DATA RAM READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM36F6 – 10
MCM36F7 – 10
Parameter
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
15
—
—
0
Max
—
10
5
Cycle Time
t
KHKH
Clock Access Time
t
KHQV
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
t
GLQV
t
t
—
—
—
5
5
5
KHQX1
3
KHQX2
t
0
5
GLQX
t
—
3
5, 6
5, 6
GHQZ
t
5
KHQZ
Clock High Pulse Width
t
5
—
—
—
KHKL
KLKH
Clock Low Pulse Width
t
5
Setup Times:
Hold Times:
NOTES:
Address
ADSP
Data In
t
t
t
2.5
AVKH
ADKH
DVKH
Write
Chip Enable
t
WVKH
t
EVKH
Address
ADSP, ADSC, ADV
Data In
t
0.5
—
ns
KHAX
t
KHADX
t
KHDX
Write
Chip Enable
t
KHWX
t
KHEX
1. Write is defined as either any BWx and SW low or WE is low.
2. Chip Enable is defined as E0 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K0 or G0.
4. G0 is a don’t care after write cycle begins. To prevent bus contention, G0 should be negated prior to start of write cycle.
5. This parameter is sampled and not 100% tested.
6. Measured at ± 200 mV from steady state.
TIMING LIMITS
The table of timing values shows either a minimum or a
Z
= 50 Ω
0
maximumlimit for each parameter. Input requirements are
specified from the external system point of view. Thus, ad-
dress setup time is shown as a minimum since the system
must supply at least that much time (even though most
devices do not require it). On the other hand, responses
from the memory are specified from the device point of
view. Thus, the access time is shown as a maximum since
the device never provides data later than that time.
OUTPUT
50
Ω
V
= 1.5 V
L
Figure 1. AC Test Load
MCM36F6•MCM36F7
MOTOROLA FAST SRAM
8
AUK [ AUK CORP ]
