Figure 32. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
XXX
XXX
in r17, PINx
INSTRUCTIONS
SYNC LATCH
PINxn
0x00
tpd, max
0xFF
r17
tpd, min
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the suc-
ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single
signal transition on the pin will be delayed between ½ and 1½ system clock period
depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 33. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock
period.
Figure 33. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
0xFF
r16
out PORTx, r16
nop
in r17, PINx
INSTRUCTIONS
SYNC LATCH
PINxn
0x00
tpd
0xFF
r17
64
AT90CAN128
4250E–CAN–12/04
ATMEL [ ATMEL ]
