ATtiny2313/V
Figure 10. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address valid
Compute Address
Address
Data
WR
Data
RD
Memory Access Instruction
Next Instruction
EEPROM Data Memory
The ATtiny2313 contains 128 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register. For a detailed descrip-
tion of Serial data downloading to the EEPROM, see page 171.
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1. A self-timing function, how-
ever, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In
heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page
19. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
The EEPROM Address
Register
Bit
7
–
6
EEAR6
R/W
X
5
EEAR5
R/W
X
4
EEAR4
R/W
X
3
EEAR3
R/W
X
2
EEAR2
R/W
X
1
EEAR1
R/W
X
0
EEAR0
R/W
X
EEAR
Read/Write
Initial Value
R
0
• Bit 7 – Res: Reserved Bit
This bit is reserved in the ATtiny2313 and will always read as zero.
15
2543F–AVR–08/04
ATMEL [ ATMEL ]
