ATmega64A
Figure 14-2. Counter Unit Block Diagram
TOVn
(Int.Req.)
DATA BUS
TOSC1
count
clear
T/C
Oscillator
clk Tn
TCNTn
Control Logic
Prescaler
direction
TOSC2
clk
bottom
top
I/O
Signal description (internal signals):
count
direction
clear
Increment or decrement TCNT0 by 1.
Selects between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock.
clkT0
top
Signalizes that TCNT0 has reached maximum value.
bottom
Signalizes that TCNT0 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the Output Compare output
OC0. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page 97.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
14.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the
Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1), the Output
Compare Flag generates an Output Compare interrupt. The OCF0 flag is automatically cleared
when the interrupt is executed. Alternatively, the OCF0 flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the WGM01:0 bits and Compare Output
mode (COM01:0) bits. The max and bottom signals are used by the Waveform Generator for
handling the special cases of the extreme values in some modes of operation (“Modes of Oper-
ation” on page 97). Figure 14-3 shows a block diagram of the Output Compare unit.
94
8160C–AVR–07/09
ATMEL [ ATMEL ]
