ATmega64A
10.3.3
Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
always is set, the WDE must be written to one to start the timed sequence.
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
10.4 Register Description
10.4.1
MCUCSR – MCU Control and Status Register(1)
The MCU Control and Status Register provides information on which reset source caused an
MCU Reset.
Bit
7
6
–
5
–
4
3
2
1
0
0x34 (0x54)
Read/Write
Initial Value
JTD
R/W
0
JTRF
R/W
WDRF
R/W
BORF
R/W
EXTRF
R/W
PORF
R/W
MCUCSR
R
0
R
0
See Bit Description
Note:
1. Only EXTRF and PORF are available in mega103 compatibility mode.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset
the MCUCSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
10.4.2
WDTCR – Watchdog Timer Control Register
Bit
0x21 (0x41)
7
6
5
–
4
WDCE
R/W
0
3
WDE
R/W
0
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
–
–
WDTCR
Read/Write
Initial Value
R
0
R
0
R
0
57
8160C–AVR–07/09
ATMEL [ ATMEL ]
