ATmega64A
Figure 27-16. Virtual Flash Page Load Register
STROBES
State
Machine
ADDRESS
Flash
EEPROM
Fuses
TDI
Lock Bits
D
A
T
A
TDO
27.9.12 Virtual Flash Page Read Register
The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of
bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the data are automati-
cally transferred from the Flash data page byte-by-byte. The first eight cycles are used to
transfer the first byte to the internal Shift Register, and the bits that are shifted out during these
eight cycles should be ignored. Following this initialization, data are shifted out starting with the
LSB of the first instruction in the page and ending with the MSB of the last instruction in the
page. This provides an efficient way to read one full Flash page to verify programming.
Figure 27-17. Virtual Flash Page Read Register
STROBES
State
Machine
ADDRESS
Flash
TDI
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
27.9.13 Programming Algorithm
All references below of type “1a”, “1b”, and so on, refer to Table 27-16.
323
8160C–AVR–07/09
ATMEL [ ATMEL ]
