ATmega64A
Figure 27-15. State Machine Sequence for Changing/Reading the Data Word
1
Test-Logic-Reset
0
1
1
1
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
Shift-DR
0
Shift-IR
0
1
Exit1-DR
0
1
1
1
Exit1-IR
0
Pause-IR
1
Pause-DR
1
0
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
1
0
0
27.9.11 Virtual Flash Page Load Register
The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of
bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically trans-
ferred to the Flash page buffer byte-by-byte. Shift in all instruction words in the page, starting
with the LSB of the first instruction in the page and ending with the MSB of the last instruction in
the page. This provides an efficient way to load the entire Flash page buffer before executing
Page Write.
322
8160C–AVR–07/09
ATMEL [ ATMEL ]
