ATmega64A
•
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see “ADCL and ADCH – The ADC Data Register” on
page 250.
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See Table 23-4 for details. If these
bits are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 23-4. Input Channel and Gain Selections
MUX4:0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
Single Ended Input Positive Differential Input
Negative Differential Input Gain
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
N/A
ADC0
ADC1
ADC0
ADC1
ADC2
ADC3
ADC2
ADC3
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC0
ADC0
ADC0
ADC0
ADC2
ADC2
ADC2
ADC2
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC2
ADC2
10x
10x
200x
200x
10x
10x
200x
200x
1x
1x
N/A
1x
1x
1x
1x
1x
1x
1x
1x
248
8160C–AVR–07/09
ATMEL [ ATMEL ]
