ATmega64A
COM21
COM20
Vcc
COM1C1
COM1C0
Modulator
0
1
( From Waveform Generator )
D
Q
1
0
OC1C
Pin
OC1C /
OC2 / PB7
( From Waveform Generator )
D
Q
Q
OC2
D
D
Q
PORTB7
DDRB7
DATA BUS
When the modulator is enabled the type of modulation (logical AND or OR) can be selected by
the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the
COMnx1:0 bit setting.
18.2.1
Timing Example
Figure 18-2 illustrates the modulator in action. In this example the Timer/Counter1 is set to oper-
ate in fast PWM mode (non-inverted) and Timer/Counter2 uses CTC waveform mode with toggle
Compare Output mode (COMnx1:0 = 1).
Figure 18-2. Output Compare Modulator, Timing Diagram
clkI/O
OC1C
(FPWM Mode)
OC2
(CTC Mode)
PB7
(PORTB7 = 0)
PB7
(PORTB7 = 1)
1
2
3
(Period)
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated
by the Output Compare unit C of the Timer/Counter1.The resolution of the PWM signal (OC1C)
is reduced by the modulation. The reduction factor is equal to the number of system clock cycles
of one period of the carrier (OC2). In this example the resolution is reduced by a factor of two.
The reason for the reduction is illustrated in Figure 18-2 at the second and third period of the
PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the
period three high time, but the result on the PB7 output is equal in both periods.
163
8160C–AVR–07/09
ATMEL [ ATMEL ]
