欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48PA-AU 参数 Datasheet PDF下载

ATMEGA48PA-AU图片预览
型号: ATMEGA48PA-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与4/8/ 16 / 32K字节的系统内可编程闪存 [8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 448 页 / 12817 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48PA-AU的Datasheet PDF文件第246页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第247页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第248页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第249页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第251页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第252页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第253页浏览型号ATMEGA48PA-AU的Datasheet PDF文件第254页  
ATmega48PA/88PA/168PA/328P  
23. Analog-to-Digital Converter  
23.1 Features  
10-bit Resolution  
0.5 LSB Integral Non-linearity  
± 2 LSB Absolute Accuracy  
13 - 260 µs Conversion Time  
Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution)  
6 Multiplexed Single Ended Input Channels  
2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Package only)  
Temperature Sensor Input Channel  
Optional Left Adjustment for ADC Result Readout  
0 - VCC ADC Input Voltage Range  
Selectable 1.1V ADC Reference Voltage  
Free Running or Single Conversion Mode  
Interrupt on ADC Conversion Complete  
Sleep Mode Noise Canceler  
23.2 Overview  
The ATmega48PA/88PA/168PA/328P features a 10-bit successive approximation ADC. The  
ADC is connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage  
inputs constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).  
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is  
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 23-1  
on page 251.  
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±0.3V  
from VCC. See the paragraph ”ADC Noise Canceler” on page 256 on how to connect this pin.  
Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage refer-  
ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.  
The Power Reduction ADC bit, PRADC, in ”Minimizing Power Consumption” on page 42 must  
be disabled by writing a logical zero to enable the ADC.  
The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-  
mation. The minimum value represents GND and the maximum value represents the voltage on  
the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V reference voltage may be con-  
nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal  
voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve  
noise immunity.  
250  
8161D–AVR–10/09  
 复制成功!