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ATMEGA48PA-AU 参数 Datasheet PDF下载

ATMEGA48PA-AU图片预览
型号: ATMEGA48PA-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与4/8/ 16 / 32K字节的系统内可编程闪存 [8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 448 页 / 12817 K
品牌: ATMEL [ ATMEL ]
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ATmega48PA/88PA/168PA/328P  
Table 19-1 contains equations for calculating the baud rate (in bits per second) and for calculat-  
ing the UBRRn value for each mode of operation using an internally generated clock source.  
Table 19-1. Equations for Calculating Baud Rate Register Setting  
Equation for Calculating Baud  
Rate(1)  
Equation for Calculating  
UBRRn Value  
Operating Mode  
f
OSC  
f
OSC  
Asynchronous Normal mode  
(U2Xn = 0)  
BAUD = -----------------------------------------  
UBRRn = ----------------------- 1  
16(UBRRn + 1)  
16BAUD  
f
OSC  
f
OSC  
Asynchronous Double Speed  
mode (U2Xn = 1)  
BAUD = --------------------------------------  
UBRRn = -------------------- 1  
8(UBRRn + 1)  
8BAUD  
f
OSC  
f
OSC  
Synchronous Master mode  
BAUD = --------------------------------------  
UBRRn = -------------------- 1  
2(UBRRn + 1)  
2BAUD  
Note:  
1. The baud rate is defined to be the transfer rate in bit per second (bps)  
BAUD  
Baud rate (in bits per second, bps)  
fOSC  
System Oscillator clock frequency  
UBRRn  
Contents of the UBRRnH and UBRRnL Registers, (0-4095)  
Some examples of UBRRn values for some system clock frequencies are found in Table 19-9  
(see page 200).  
19.3.2  
Double Speed Operation (U2Xn)  
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has  
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.  
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling  
the transfer rate for asynchronous communication. Note however that the Receiver will in this  
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock  
recovery, and therefore a more accurate baud rate setting and system clock are required when  
this mode is used. For the Transmitter, there are no downsides.  
179  
8161D–AVR–10/09  
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